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Simulink as a Test Bench

Communications During Test Bench Cosimulation

When you link the HDL simulator with a Simulink® application, the simulator functions as the server, as shown in the following figure.

In this case, the HDL simulator responds to simulation requests it receives from cosimulation blocks in a Simulink model. You begin a cosimulation session from Simulink. After a session is started, you can use Simulink and the HDL simulator to monitor simulation progress and results. For example, you might add signals to a wave window to monitor simulation timing diagrams.

As the following figure shows, multiple cosimulation blocks in a Simulink model can request the service of multiple instances of the HDL simulator, using unique TCP/IP socket ports.

When you link the HDL simulator with a Simulink application, the simulator functions as the server. Using the HDL Verifier™ communications interface, an HDL Cosimulation block cosimulates a hardware component by applying input signals to and reading output signals from an HDL model under simulation in the HDL simulator.


Vivado® users: Simulink executes the cosimulation as a single process, so there is no need to communicate with an HDL server.

This figure shows a sample Simulink model that includes an HDL Cosimulation block. The connection is using shared memory.

The HDL Cosimulation block models a Manchester receiver that is coded in HDL. Other blocks and subsystems in the model include the following:

  • Frequency Error Range block, Frequency Error Slider block, and Phase Event block

  • Manchester encoder subsystem

  • Data alignment subsystem

  • Inphase/Quadrature (I/Q) capture subsystem

  • Error Rate Calculation block from the Communications Toolbox™ software

  • Bit Errors block

  • Data Scope block

  • Constellation Diagram block from the Communications Toolbox software

For information on getting started with Simulink software, see the Simulink online help or documentation.

How Simulink Drives Cosimulation Signals

Although you can bind the output ports of an HDL Cosimulation block to any signal in an HDL model hierarchy, you must use some caution when connecting signals to input ports. You want to verify that the signal you are binding to does not have other drivers. If it does, use resolved logic types; otherwise you may get unpredictable results.

If you need to use a signal that has multiple drivers and it is resolved (for example, it is of VHDL® type STD_LOGIC) , Simulink applies the resolution function at each time step defined by the signal's Simulink sample rate. Depending on the other drivers, the Simulink value may or may not get applied. Furthermore, Simulink has no control over signal changes that occur between its sample times.


Verify that signals used in cosimulation have read/write access. You can check read/write access through the HDL simulator—see HDL simulator documentation for details.

This rule applies to all signals on the Ports, Clocks, and Simulation panes and to signals added to the model in any other manner.

Multirate Signals During Test Bench Cosimulation

HDL Verifier software supports the use of multirate signals, signals that are sampled or updated at different rates, in a single HDL Cosimulation block. An HDL Cosimulation block exchanges data for each signal at the Simulink sample rate for that signal. For input signals, an HDL Cosimulation block accepts and honors all signal rates.

The HDL Cosimulation block also lets you specify an independent sample time for each output port. You must explicitly set the sample time for each output port, or accept the default. Using this setting lets you control the rate at which Simulink updates an output port by reading the corresponding signal from the HDL simulator.

Continuous Time Signals

Use the Simulink Zero-Order Hold block to apply a zero-order hold (ZOH) on continuous signals that are driven into an HDL Cosimulation block.

HDL Cosimulation Block Features for Test Bench Simulation

The HDL Verifier HDL Cosimulation block links hardware components that are concurrently simulating in the HDL simulator to the rest of a Simulink model.

You can link Simulink and the HDL simulator in two possible ways:

  • As a single HDL Cosimulation block fitted into the framework of a larger system-oriented Simulink model.

  • As a Simulink model made up of a collection of HDL Cosimulation blocks, each representing a specific hardware component.

The block mask contains panels for entering port and signal information, setting communication modes, adding clocks (Xcelium™ and ModelSim® only), specifying pre- and post-simulation Tcl commands (Xcelium and ModelSim only), and defining the timing relationship.

After you code one of your model's components in VHDL or Verilog® and simulate it in the HDL simulator environment, you integrate the HDL representation into your Simulink model as an HDL Cosimulation block. There is one block for each supported HDL simulator. These blocks are located in the Simulink Library, within the HDL Verifier block library. As an example, the block for use with Mentor Graphics® ModelSim is shown in the next figure.

You configure an HDL Cosimulation block by specifying values for parameters in a block parameters dialog box. The HDL Cosimulation block parameters dialog box consists of tabbed panes that specify the following information:

  • Ports Pane: Block input and output ports that correspond to signals, including internal signals, of your HDL design, and an output sample time.

  • Connection Pane: Type of communication and related settings to be used for exchanging data between simulators.

  • Timescales Pane: The timing relationship between Simulink software and the HDL simulator.

  • Clocks Pane (Xcelium and ModelSim only): Optional rising-edge and falling-edge clocks to apply to your model.

  • Simulation Pane (Xcelium and ModelSim only): Tcl commands to run before and after a simulation.

For more detail on each of these panes, see the HDL Cosimulation reference page.