HDL Verifier™ lets you test and verify VHDL® and Verilog® designs for FPGAs, ASICs, and SoCs. You can verify RTL with testbenches running in MATLAB® or Simulink® using cosimulation with Siemens® Questa® or ModelSim®, Cadence® Xcelium™, and the Xilinx® Vivado® simulator. You can reuse these same testbenches with FPGA development boards to verify hardware implementations.
HDL Verifier generates SystemVerilog verification models for RTL testbenches and complete Universal Verification Methodology (UVM) environments. These models run natively in the Questa, Xcelium, and Vivado simulators, as well as Synopsys® VCS via the SystemVerilog Direct Programming Interface (DPI).
HDL Verifier provides tools for debugging and testing implementations on Xilinx, Intel®, and Microchip boards from MATLAB. You can insert probes into designs and set trigger conditions to upload internal signals into MATLAB for visualization and analysis.
Learn the basics of HDL Verifier
Cosimulation between HDL simulators and MATLAB and Simulink
Connect an FPGA board with MATLAB and Simulink for verification and debug of hardware designs
Generation of UVM or SystemVerilog DPI components
Generate test benches to verify HDL code generated with HDL Coder™
Generation of SystemC TLM virtual prototypes
Support for third-party hardware, such as Xilinx, Intel, and Microchip FPGA boards