Code Verification and Validation with PIL

Introduction

In this example you will learn how to configure a Simulink model to run Processor-In-the-Loop (PIL) simulation. In a PIL simulation, the generated code runs on the NXP FRDM-KL25Z Board. The results of the PIL simulation are transferred to Simulink to verify the numerical equivalence of the simulation and the code generation results. The PIL verification process is a crucial part of the development cycle to ensure that the behavior of the deployment code matches the design.

This example introduces the Simulink® code generation and verification workflow by showing you how to:

Prerequisites

We recommend completing Getting Started with Simulink Coder Support Package for NXP FRDM-KL25Z Board.

Required Products

Embedded Coder

Required Hardware

To run this example you will need the following hardware:

On Mac:

On Windows®:

Note:

OS Specific Limitations

On Mac:

External mode simulation is supported only through UART1 or UART2.

On Windows:

External mode simulation is supported through all UART communication interfaces.

Task 1 - Choose a Serial Communication Interface for PIL Simulation

The Simulink Coder Support Package for NXP FRDM-KL25Z Board supports three different serial communication interfaces for PIL: UART0, UART1, and UART2. Please note that, on Mac platforms, PIL simulation over UART0 is supported only on Mac version 'El Capitan'.

The UART0 serial communication interface is accessible through either the mini USB port labeled with openSDA on the NXP FRDM-KL25Z board or the onboard GPIO pins for UART0. Using UART0 via the mini USB port does not require any additional cables or hardware, besides a USB type A to Mini-B cable that is used to connect the NXP FRDM-KL25Z board to the host computer. To use the UART0 through the other GPIO pins on NXP FRDM-KL25Z board, additional hardware, for example, a USB TTL-232R adapter.

The UART1 and UART2 serial communication interfaces are accessible only through pins on the NXP FRDM-KL25Z board. Using these interfaces requires additional hardware, for example, a USB TTL-232R adapter, to perform PIL simulations.

1. Choose a serial communication interface using the steps below:

2. Choose the Tx and Rx GPIO pins for the selected serial communication interface:

3. Connect to the hardware. Follow the steps below based on the serial interface you selected:

For UART0:

For UART1:

For UART2:

4. Once you complete the steps above, a new serial COM port should be available for use on your host computer. To find the COM port associated with your adapter cable, follow the steps below:

On Windows:

On Mac:

5. Open your model configured for code generation on a NXP FRDM-KL25Z board. In Configuration Parameters > Hardware Implementation > Target Hardware Resources > PIL > Serial port, enter the Serial port field with the COM port number noted in the previous step.

For example, on Windows enter COM27 in the Serial port field, while on Mac enter /dev/cu.usbmodem1442.

open_system('freedomboard_pil_block');

Task 2 - Verify the Generated Code for a Subsystem Using a PIL Block

This example shows how to use a PIL block for subsystem code verification. With this approach:

1. Open the PIL Block model. This model is configured for the NXP FRDM-KL25Z target. The objective here is to create a PIL block out of the Controller subsystem that you will run on the NXP FRDM-KL25Z board.

2. Choose a PIL communication interface by following the steps in Task 1 - Choose a Serial Communication Interface for PIL Simulation of this example.

3. Follow the below steps to enable PIL:

Note: Ensure that Use Embedded Coder features is enabled under Hardware Implementation > Advanced parameters

a. Go to the Modeling tab and press Ctrl+E to open Configuration Parameters dialog box.

b. Go to Code Generation > Verification > Advanced parameters and select PIL.

4. Follow the below steps to create a PIL block for the Controller subsystem:

a. Right click on the Controller subsystem and select Deploy this Subsystem to Hardware.

b. In the Build code for SubsystemController dialog box, click Build.

5. Follow the below steps to run the PIL simulation:

6. You can switch between the original and PIL block subsystems by double clicking on the Manual Switch block. Double click on the Numerical Differences block to see the difference between the simulated Controller subsystem and the PIL block running on the NXP FRDM-KL25Z board.

open_system('freedomboard_model_pil_block');

Task 3 - Verify Referenced Model Code Using PIL

This example shows how to verify the generated code for a referenced model by running a PIL simulation. With this approach:

1. Open the Model Block PIL model. This model is configured for NXP FRDM-KL25Z target. The model contains two Model blocks that both point at the same referenced model. You will configure one of the Model blocks to run in PIL simulation mode and the other in normal mode.

2. Choose a PIL serial communication interface for the Model Block PIL and Referenced model by following the steps in Task 1 - Choose a Serial Communication Interface for PIL Simulation in this example.

3. Follow the below steps to configure and run the CounterA Model block in PIL mode:

a. Right click on block CounterA and select Block Parameters (ModelReference)

b. In the CounterA block parameter, Select Simulation mode as Processor-in-the-Loop(PIL)

c. Go to Simulation tab and Run

4. When the model starts running, Scope1 displays the PIL simulation output running on the NXP FRDM-KL25Z board while Scope2 shows the normal mode simulation output.

open_system('freedomboard_top_model_pil');

Task 4 - Verify Top Model Code Using PIL

This example shows how to verify the generated code for a model by running a PIL simulation. With this approach:

1. Open the Top Model PIL model. This model is configured for the Freecale FRDM-KL25Z target.

2. Choose a PIL serial communication interface by following the steps in Task 1 - Choose a Serial Communication Interface for PIL Simulation in this example.

3. Go to Apps tab and search SIL/PIL.

4. Select Processor-in-the-Loop(PIL) from the SIL/PIL Mode drop-down and click Run Verification.

5. When the PIL simulation is completed, a logsOut variable is created in the base workspace. The logsOut data contains PIL simulation results. You can access the logged data for signals count_a and count_b using the following commands: