Post-Layout Verification of Parallel Link Projects
Post-layout verification allows you to verify the performance of your actual routed system against the design guidelines or specification rules. You can edit the vias and stackups and control the padstack models. You can also verify your design using PCB models. You can create topologies from extracted PCB data for pre-layout analysis.
Note
You need a RF PCB Toolbox™ license for the post-layout workflow.
Apps
| Parallel Link Designer | Analyze PCB designs for parallel link applications (Since R2021b) |
| Signal Integrity Viewer | View the signal integrity results of Serial Link Designer or Parallel Link Designer apps (Since R2021b) |
Topics
- Post-Layout Verification of Parallel Link
Verify system-level SI and timing margins of PCB design databases.
- Post-Layout Verification Workflow
Set up stimulus patterns, SPICE options, and select the nets for simulation during post-layout verification.
- Stackup and Extraction Control in Parallel Link Project
Edit stackups and control padstack models.
- Via and Stackup Management in Parallel Link Project
Manage vias and stackups using Stackup Editor and PadStack Editor.
- Run Incremental Simulation
Run additional nets during post-layout validation without deleting existing simulations.
- Post-Layout to Pre-Layout Extraction
Create topologies from extracted PCB data.
Featured Examples
Post-Layout of DDRx Interface with CPU and DIMMs
Show how to use the Parallel Link Designer app to set up a post-layout analysis of a DDRx interface on a Main Board having a CPU connected to two DIMM slots to verify that waveform quality and timing margins are met by the PCB database. Many of the steps illustrated in this example are also applicable to Serial Link Designer for post-layout analysis of SerDes links.
