Unbuffered DDR2 with PLL Architectural Kit
Implement an unbuffered DDR2 interface with PLL clock buffer for pre-layout analysis or post-layout verification.
This unbuffered DDR2 with PLL architectural signal integrity kit includes all transfer nets, timing models, waveform processing levels and generic models for an unbuffered DDR2 interface with PLL clock buffer. This includes generic buffer models for the DDR2 controller, PLL and SDRAM, along with fully functional timing models and complete waveform processing levels. You can modify the kit to match your exact implementation. Then, perform complete pre-layout solution space analysis and/or full post-layout verification for waveform quality and timing margins.
Open Unbuffered DDR2 with PLL Kit
Open the unbuffered DDR2 with PLL kit in the Parallel Link Designer app using the
For more information about the unbuffered DDR2 with PLL architectural signal integrity kit, including block diagrams, system configurations, transfer nets, and libraries, along with instructions on how to customize the kit for a specific implementation, refer to the document DDR2_Unbuffered_With_PLL.pdf that is attached to this example as a supporting file.