PCIe-3 Compliance Kit
Test the compliance of simulation models and topologies to the PCI Express generation 3 (PCIe-3) specification.
The PCIe-3 signal integrity kit includes all the transfer nets, topologies, generic buffer models and compliance rules for a PCIe-3 high-speed SerDes interface. This includes PCIe-3 technology IBIS-AMI models for the SerDes transmitter and receiver, PCIe-3 compliance masks and transfer nets preconfigured for TX and RX characterization that are customizable for a specific PCIe-3 add-in card (AIC), system board (SB), and PCIe-3 embedded channel.
This kit enables you to insert a channel design and characterize and validate its performance using the specification masks to determine if the channel has a high confidence of success. If the channel does not meet the compliance masks or BER estimates, further investigation or redesign, along with simulation, will need to be performed to determine possible changes to meet compliance.
Open PCIe-3 Kit
Open the PCIe-3 kit in the Serial Link Designer app using the
Project Name: PCIe_Gen3_NVMe
Interface Name: PCIe_Gen3
Target Operating Frequency: 8.0 Gb/s, 4.0 GHz (Nyquist) (UI = 125 ps)
The PCIe-3 kit defines four schematic sets:
All_Sheets: All schematic sheets
AIC: Schematic sheets for add-in card design
SB_Slot: Schematic sheets for system board with slot design
SB_Emb: Schematic sheets for system board embedded design
For more information about the PCIe-3 channel compliance schematics, transfer net properties and compliance rules, refer to the document PCIe_gen3.pdf that is attached to this example as a supporting file.