PCIe-5 Compliance Kit
Test the compliance of simulation models and topologies to the PCI Express generation 5 (PCIe-5) specification.
This PCIe compliance signal integrity kit includes all the transfer nets, topologies, generic buffer models and compliance rules for a PCIe-5 high-speed SerDes interface. This includes PCIe-5 technology IBIS-AMI models for the SerDes transmitter and receiver, PCIe-5 compliance masks and transfer nets preconfigured for TX and RX characterization that are customizable for a PCIe-5 embedded channel.
This kit enables you to insert a channel design and characterize and validate its performance using the specification masks to determine if the channel has a high confidence of success. If the channel does not meet the compliance masks or BER estimates, further investigation or redesign, along with simulation, will need to be performed to determine possible changes to meet compliance.
Open PCIe-5 Kit
Open the PCIe-5 kit in the Serial Link Designer app using the
openSignalIntegrityKit helper function.
Project Name: PCIe_Gen5_NVMe
Interface Name: PCIe_Gen5
Target Operating Frequency: 32.0 Gb/s; 16.0 GHz (Nyquist) (UI = 31.25 ps)
The PCIe-5 kit defines five schematic sets:
All_Sheets: All schematic sheets
Cal_Channel_Ref_Design_32Gbps: Base Specification Reference Design for 32 Gbps
Channel_Tolerancing: Calibration Channel Stressed RX Testing
Compliance_Board_Testing: Network Characteristics for Calibration Channel Models and Reference Design Models
Tx_and_Rx_Pkg_Tests: Testing of Tx and Rx Characteristics and Package Model
For more information about the PCIe-5 channel compliance schematics, transfer net properties and compliance rules, refer to the document PCIe_gen5.pdf that is attached to this example as a supporting file.