Switch Case Action Subsystem

Subsystem whose execution is enabled by Switch Case block

• Library:

• Simulink / Ports & Subsystems

• 

Description

The Switch Case Action Subsystem block is a Subsystem block preconfigured as a starting point for creating a subsystem whose execution is controlled by a Switch Case block. The input port to a Switch Case block selects a case defined using the Case conditions parameter. Depending on input value and case selected, an action signal is sent to execute a Switch Case Action Subsystem block. Execution of the subsystem is controlled by an Action Port block placed inside the subsystem.

Simulink^® ignores a priority set on an Switch Case Action Subsystem block. Instead, set the priority on the Switch Case block that initiates execution of the subsystem.

All blocks in a Switch Case Action Subsystem block must run at the same rate as the driving Switch Case block. You can achieve this requirement by setting each block sample time parameter to be either inherited (-1) or the same value as the Switch Case block sample time.

Merge signals from Switch Case Subsystem blocks

This example shows how to create a one signal from multiple subsystem output signals. The Switch Case block selects the execution of one If Action Subsystem block from a set of subsystems. Regardless of which subsystem the Switch Case block selects, you can create a one resulting signal with a Merge block. To open the model, see ex_switch_case_block.

Ports

Input

In1 — Signal input to a subsystem block

scalar | vector | matrix

Placing an Inport block in a subsystem block adds an external input port to the block. The port label matches the name of the Inport block.

Use Inport blocks to get signals from the local environment.

Data Types: half | single | double | int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64 | Boolean | fixed point | enumerated | bus

Action — Control signal input to a subsystem block

scalar | vector | matrix

Placing an Action Port block in a subsystem block adds an external input port to the block and changes the block to a Switch Case Action Subsystem block.

Dot-dash lines from a Switch Case block to an Switch Case Action Subsystem block represent action signals. An action signal is a control signal connected to the action port of an Switch Case Action Subsystem block. A message on the action signal initiates execution of the subsystem.

Data Types: action

Output

Out1 — Signal output from a subsystem

scalar | vector | matrix

Placing an Outport block in a subsystem block adds an output port from the block. The port label on the subsystem block is the name of the Outport block.

Use Outport blocks to send signals to the local environment.

Data Types: half | single | double | int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64 | Boolean | fixed point | enumerated | bus

Model Examples

Simulink Subsystem Semantics

This set of examples shows different types of Simulink® Subsystems and what semantics are used when simulating these Subsystems. Each example provides a description of the model and the subtleties governing how it will be executed.

Open Model

Block Characteristics

Data Types	Booleana | busa | doublea | enumerateda | fixed pointa | halfa | integera | singlea | stringa
Direct Feedthrough	no
Multidimensional Signals	limiteda
Variable-Size Signals	limiteda
Zero-Crossing Detection	no
a Actual data type or capability support depends on block implementation.

Extended Capabilities

C/C++ Code Generation

Generate C and C++ code using Simulink® Coder™.

Actual data type or capability support depends on block implementation.

HDL Code Generation

Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

Architecture	Description
Module (default)	Generate code for the subsystem and the blocks within the subsystem.
BlackBox	Generate a black box interface. The generated HDL code includes only the input/output port definitions for the subsystem. Therefore, you can use a subsystem in your model to generate an interface to existing, manually written HDL code. The black-box interface generation for subsystems is similar to the Model block interface generation without the clock signals.
No HDL	Remove the subsystem from the generated code. You can use the subsystem in simulation, however, treat it as a “no-op” in the HDL code.

HDL Block Properties

General
AdaptivePipelining	Automatic pipeline insertion based on the synthesis tool, target frequency, and multiplier word-lengths. The default is inherit. See also AdaptivePipelining (HDL Coder).
BalanceDelays	Detects introduction of new delays along one path and inserts matching delays on the other paths. The default is inherit. See also BalanceDelays (HDL Coder).
ClockRatePipelining	Insert pipeline registers at a faster clock rate instead of the slower data rate. The default is inherit. See also ClockRatePipelining (HDL Coder).
ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is 0. For more details, see ConstrainedOutputPipeline (HDL Coder).
DistributedPipelining	Pipeline register distribution, or register retiming. The default is off. See also DistributedPipelining (HDL Coder).
DSPStyle	Synthesis attributes for multiplier mapping. The default is none. See also DSPStyle (HDL Coder).
FlattenHierarchy	Remove subsystem hierarchy from generated HDL code. The default is inherit. See also FlattenHierarchy (HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. For more details, see InputPipeline (HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. For more details, see OutputPipeline (HDL Coder).
SharingFactor	Number of functionally equivalent resources to map to a single shared resource. The default is 0. See also Resource Sharing (HDL Coder).
StreamingFactor	Number of parallel data paths, or vectors, that are time multiplexed to transform into serial, scalar data paths. The default is 0, which implements fully parallel data paths. See also Streaming (HDL Coder).

Target Specification

This block cannot be the DUT, so the block property settings in the Target Specification tab are ignored.

Fixed-Point Conversion

Design and simulate fixed-point systems using Fixed-Point Designer™.

Actual data type support depends on block implementation.

Version History

Introduced before R2006a