Check for consistency in model element names
R2026bCheck ID:
mathworks.jmaab.jc_0602
Guideline: jc_0602: Consistency in model element names
Description
Checks if the model elements connected to a signal are following consistent naming.
The following names must be matched exactly when directly connected with signal lines:
Exception 1: The name of a signal line connected to one of the below subsystems can have a different name to that of the subsystem port label name:
Reusable subsystems
Subsystems linked to a library
Exception 2: If a combination of Inport blocks, Outport blocks, and other blocks have the same block name, use a suffix or prefix for the Inport and Outport blocks for consistent naming. This can be configured through Model Advisor Configuration Editor.
This check requires a Simulink® Check™ license.
Check Parameterization
This check does not include sub-checks because the MAB modeling guideline provides only one sub ID.
For reference, the MAB guideline sub ID(s) that are recommended for use by the NA-MAAB and JMAAB modeling standards organizations are:
NA-MAAB — No recommendations
JMAAB — a
You can configure the following parameters to customize the check action:
| Input Parameter | Default Value |
|---|---|
| Consistent naming format for combination of Inport and Outport blocks | Prefix(<Prefix_tag><Signal_name><Sequence>) or Suffix(<Signal_name><Sequence><Suffix_tag>) |
| Prefix/Suffix tag for Inport | IN_ (Default value, can be configured) |
| Prefix/Suffix tag for Outport | OUT_ (Default value, can be configured) |
Results and Recommended Actions
| Condition | Recommended Action |
|---|---|
| One or more model elements are not consistent with the connected signal name. | Rename the deviating model elements to match the signal name, or be consistent with Inport/Outport blocks. |
Tip
For Bus Element Ports, the check evaluates naming consistency based on the associated bus and element names, not the block name. When naming signals connected to a Bus Element Port:
Use either the leaf element name (for example,
sig2) or a signal name derived from the bus and element hierarchy (for example,InBus_sig1_sig2).When a Bus Element Port is connected to a Subsystem, only the full bus passes through the interface. In this case, the signal name must match the bus name (for example,
InBus).
Capabilities and Limitations
Runs on library models.
Analyzes content in masked subsystems. By default, the input parameter Look under masks is set to
graphical.Allows exclusions of blocks or charts.
Does not check referenced models.
Edit-Time Checking
This check is supported by edit-time checking.