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Parameter Identification

This example shows how to tune parameters using parameter configuration file for Simulink Design Verifier analysis. The model contains the parameter control_mode that enables the active controller and selects its output to be the model output. Simulink Design Verifier treats this parameter as an input that is constrained to be either 1 or 2 and generates the appropriate value for each test case.

open_system('sldvdemo_param_identification');