Resolve Undecided Objectives When Analysis Is Interrupted or Times Out

Issue

If Simulink^® Design Verifier™ analysis is unable to determine an outcome in the allotted time, the objectives remain undecided. This happens when either the software exceeded its analysis time limit, or you aborted the analysis before it completed processing these objectives. For more information, see Undecided Objectives Due to Incomplete Analysis.

When the analysis is unable to determine the outcome in the allotted time, it displays this error message in the Diagnostic Viewer:

Simulink Design Verifier has exceeded the maximum processing time. This may have impacted the results. Rerun and complete the analysis after extending the time limit. You can extend the time limit by modifying the "Maximum analysis time" edit field on the Design Verifier pane of the configuration dialog or by modifying the "MaxProcessTime" attribute of the options object.

Possible Solutions

All guidelines and considerations for analyzing large models apply here. Try one of these solutions:

Increase the Analysis Time

Increase the maximum analysis time for the model.

In the Configuration Parameters dialog box, in the Design Verifier pane, set the desired value in seconds for Maximum analysis time.

Resume Analysis from Last Stopped State

If model configuration parameter Rebuild model representation is set to If change is detected, you can restart the analysis from the point where it stopped. To extend the analysis duration, run the analysis again with the same timeout value to add the specified amount of time to your previous analysis session. (since R2026a)

Simplify the Data Types

Models that use the double data type may be more complex to analyze because of the wide range of values and the need to account for rounding effects. Simplify the data types to improve the precision of model representation generated from the model. For example, you can use smaller data types, such as fixed-point, integer, or Boolean, where appropriate.

Simplified data types avoid unnecessary cast operators during data type conversion. This approach helps you avoid nonlinear operations during the analysis. Timers and counters within the model yield more precise results if corresponding variables are of an integer data type. For more information, see Manage Model Data to Simplify the Analysis.

Constrain Data Type Ranges

Constraining data type ranges can reduce the search space for analysis. Limiting a data type to a set of discrete values helps in linearization of nonlinear operations. To constrain or discretize the data type range:

Add minimum and maximum values in model inputs.
Use the Test Condition block or the sldv.assume function to discretize the range of inputs or intermediate signals.

For more information, see Manage Model Data to Simplify the Analysis.

Analyze Model Components Separately

Analyze each referenced model in the hierarchy individually to identify the issue that affects the results. This approach helps to generate test cases suitable for unit testing during the test generation analysis.

For design error detection, analyzing model components separately helps to detect dead logic or objectives without run-time errors much faster due to reduction in analysis complexity. For more information, see Extract Subsystems for Analysis.

Use a Bottom-Up Approach for Analysis

If you have large model, consider a bottom-up approach for the analysis. In this approach, Simulink Design Verifier analyzes all the components in the model independently. In this approach, the software analyzes smaller model components first and then analyzes larger components. For more information, see Bottom-Up Approach to Model Analysis.

Investigate Model with Timers and Counters

If the objectives in your model are impacted by timers and counters and shows undecided status, consider workarounds that search through sequences of states to find input values that satisfy specific objectives. For more information, see Analyze Models with Counters and Timers.

Use Seed Test Case to Reanalyze the Model

Seed test cases are input scenarios that provide specific input values that allow Simulink Design Verifier analysis to solve complex or nonlinear computations and reach parts of the model that might otherwise be difficult to access, such as logic that only activates after a timer or counter passes a certain threshold. This approach prevents unnecessary delays in analysis. Simulink Design Verifier analysis uses this seed test case to analyze downstream logic once the timer expires. For more information, see:

Filter Out Analyzed Objectives

Filter out objectives that are already covered by existing test data from analysis. Due to this exclusion, Simulink Design Verifier focus its analysis on the remaining objectives. If the excluded objectives are complex, this approach prevents them from causing slowness in the analysis. For more information, see Extend an Existing Test Suite.

You can also use a filter file to remove complex objectives from the analysis. For more information, see Exclude and Justify Objectives for Design Error Detection.