What Is Component Verification?

When testing models, you may find that your models do not meet design requirements. Resolving these problems requires additional component verification. Component verification refers to a process that tests a design component in a model. For more information, see Component Verification.

Component Verification Approaches

Component verification lets you test a design component in your model using either of the following approaches:

• Within the context of the model that contains the component — Using systematic simulation of closed-loop controllers requires that you verify components within a control system model. Doing so lets you test the control algorithms with your model. This approach is called system analysis.

• As standalone components — For a high level of confidence in the component algorithm, verify the component in isolation from the rest of the system. This approach is called component analysis.

  Verifying standalone components provides three advantages:

  • You can use analysis to focus on portions of the design that you cannot test because of the physical limitations of the system being controlled.

  • You can use this approach for open-loop simulations to test the plant model without feedback control.

  • You can use this approach when the model is unavailable or when you need to simulate a control system model in accelerated mode for performance reasons.

Simulink Design Verifier Tools for Component Verification

By isolating the component to verify, and using tools that Simulink^® Design Verifier™ provides, you create test cases that let you expand the scope of the testing for large models. This expanded testing helps you accomplish the following:

• Achieve 100% model coverage — If certain model components do not record 100% coverage, the top-level model cannot achieve 100% coverage. By verifying these components individually, you can create test cases that fully specify the component interface, allowing the component to record 100% coverage.

• Debug the component — To verify that each model component satisfies the specified design requirements, you can create test cases that verify that specific components perform as designed.

• Test the robustness of the component — To verify that a component handles unexpected inputs and calculations properly, you can create test cases that generate data. Then, test the error-handling capabilities in the component.

Functions for Component Verification

The Simulink Design Verifier software provides several functions that facilitate the tasks associated with component verification.

Function	Task
sldvlogsignals	Simulate a Simulink model and log input signals to a Model block in the model. If you modify the test cases in the Signal Editor harness model, use this approach for logging input signals to the harness model itself.
sldvmakeharness	Create a harness model for a component, using logged input signals if specified, or using the default signals. For more information about harness models, see Manage Simulink Design Verifier Harness Models.
sldvmergeharness	Merge test cases from several harness models into a single harness model.
sldvextract	Extract an atomic subsystem or atomic subchart into a new model.
sldvruntest	Simulate a model, executing the specified test cases to record model coverage and outport values.
sldvruncgvtest	Invoke the Code Generation Verification (CGV) API, and execute the specified test cases on the generated code for the model. Note To execute a model in different modes of execution, use the CGV API to verify the numerical equivalence of results. For more information about the CGV API, see Programmatic Code Generation Verification (Embedded Coder).

Component verification functions do not support the following Simulink features:

• Variable-step solvers for sldvruntest

• Component interfaces that contain:

  • Variable-size signals

  • Multiword fixed-point data types larger than 128 bits