Vector To DAC
Convert vector inputs to concatenated 16-bit DAC output samples
SoC Blockset Support Package for Xilinx Devices / SDR / RFSoC
The Vector To DAC block converts the vector input to concatenated 16-bit digital-to-analog converter (DAC) output samples.
The block accepts a vector of N samples through the vectorData input port and outputs 16-bit samples packed into N x 16 bits through the dacData output port based on the N value. N is the length of the input word.
vectorData — DAC data samples in vector form
DAC data samples, specified as a column vector. This input must be an N-element column vector of N samples, where the first sample is the lower significant bit (LSB), and the last sample is the most significant bit (MSB). N is the length of the input word set by the Shortened input word length parameter.
dacData — DAC data samples
DAC data samples, returned as a scalar. The block returns N x 16 bit output samples, where N is the length of the input word set by the Shortened input word length parameter.
Shortened input word length — Length of input word
16 (default) | integer from 1 to 16
Specify the input word length as an integer from 1 to 16. This parameter sets the required input vector size and the bit width of the output samples.
HDL Code Generation
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Introduced in R2020b