Video Capture USB
Import live video frames from one or more USB cameras on Zynq-based hardware
Since R2024b
Add-On Required: This feature requires the SoC Blockset Support Package for AMD FPGA and SoC Devices add-on.
Libraries:
SoC Blockset Support Package for AMD FPGA and SoC Devices /
MPSoC /
ZCU106
SoC Blockset Support Package for AMD FPGA and SoC Devices /
MPSoC /
ZCU102
Description
The Video Capture USB block captures video frames from a Zynq®-based board that has one or more USB video device class (UVC) cameras or Basler USB 3.0 cameras, and imports the frames into your Simulink® model. The reference design programs the FPGA with an image that includes a USB camera interface, data path multiplexers, video format conversions, and a video test pattern generator (TPG). You can control these data path and conversion options from the Video Capture USB block.
Examples
Getting Started with USB Camera
Capture video into Simulink from a USB camera connected to your FPGA board.
Limitations
To use this block, in the hardware setup, set Hardware Board to
Xilinx Zynq UltraScale+ MPSoC ZCU106 Evaluation KitorXilinx Zynq UltraScale+ MPSoC ZCU102 Evaluation Kitand set Add-on Card toUSB Cameras. If you have a Basler USB 3.0 camera, you must download Pylon 6.2.0 Camera Software Suite Linux ARM 64 bit. Download instructions are provided in the hardware setup. If you do not have a Basler USB 3.0 camera, you can click the Skip this step check box on the Pylon® screen in hardware setup.Use the IP core workflow to generate HDL code. This block does not support using the SoC Builder tool. For more information on workflows, see SoC Generation Workflows.
In the HDL Workflow Advisor tool, in step 1.1, set Target platform to
Xilinx Zynq UltraScale+ MPSoC ZCU106 Evaluation KitorXilinx Zynq UltraScale+ MPSoC ZCU102 Evaluation Kit. In step 1.2, set Reference design toUSB Camera Receive Path.
Ports
Output
Parameters
Ethernet address of an SoC device connected to your host machine.
The video stream through the FPGA logic and ARM® processor can start with input video from the USB port of the SoC device or with generated video from the test pattern generator (TPG). Use the Scan button to detect one or more cameras connected to the USB port of your SoC device. The drop-down menu updates with the names of the detected cameras.
detected UVC camera name — Camera connected to the USB input port on the SoC device. The Frame size parameter menu updates to match the available resolutions from the detected camera.
USB 3.0 Basler Camera— Camera connected to the USB input port on the SoC device. The Frame size parameter menu updates to the list of supported resolutions.Test pattern generator— On-board TPG. The TPG on the SD card creates input frames at the requested resolution. Select a fixed color bar pattern or a moving ball in the Test pattern parameter. When you select the TPG, you do not need a camera connected to the USB port on the SoC device.
The test pattern generator on the SD card creates input frames at the requested resolution.
SMPTE color bars—
Moving ball—
Select from the supported resolutions available on your detected camera.
To use a frame size greater than 2k resolution, you must configure the FPGA reference design to use 2-pixel-per-clock streaming. The default reference design loaded during setup uses 2-pixel-per-clock streaming. You can configure the number of pixels per clock in Step 1.2 of the HDL Workflow Advisor. For details, see Target FPGA on Zynq Hardware.
For a Basler USB 3.0 camera, or the test pattern generator, these resolutions are available:
320x240p640x480p1280x720p1920x1080p
The block calculates available frame rates based on the supported resolutions available from the detected camera. The block can achieve up to 120 fps for resolutions below 1080p.
The block sets the Simulink sample time for the captured video frames to 1/Frame rate.
Specify the format of the pixel stream as one of these values.
RGB— Three 8 bit color components per pixel, which is 24 bits per pixel total.YCbCr 4:2:2(default) — Also known as YUYV. An 8 bit Y component and an interleaved 8 bit CbCr component. The effective pixel size is 16 bits. The block returns the component frames on the Y, Cb, and Cr output ports.
Specify the format of the pixel stream as one of these values.
RGB— Three 8 bit color components per pixel, which is 24 bits per pixel total.YCbCr 4:2:2(default) — Also known as YUYV. An 8 bit Y component and an interleaved 8 bit CbCr component. The effective pixel size is 16 bits. The block returns the component frames on the Y, Cb, and Cr output ports.
Select this parameter to bypass the user logic section of the FPGA and send the input video frames directly to the host.
Specify the RGB output stream format as one of these values.
Separate color signals— The block returns separate height-by-width matrices for each color component. In this case, the block has R, G, and B output ports.One multidimensional signal— The block returns a single 3-by-height-by-width matrix. In this case, the block has an Image output port.
Dependencies
To enable this parameter, set Pixel format to
RGB.
Version History
Introduced in R2024b
