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Getting Started with PPU Acceleration for Infineon AURIX TC4x Microcontrollers

This example shows how you can use SoC Blockset™ Support Package for Infineon AURIX Microcontrollers to improve performance using PPU accelerator and implement two-way Interprocess communication between TriCore0 and Parallel Processing Unit (PPU) on an Infineon® AURIX™ microcontroller. This example uses a top-level model and two referenced models for two-way communication between a TriCore and PPU. You can deploy the code on an Infineon AURIX TC4xx TriBoard and observe that the LEDs that you configured for each core are blinking.

Open Top-Level Model and Perform Hardware Mapping of IPC Event and Peripherals

Open the top-level tc4x_Ipc_PPU_TC0_topModel model.

The model consists of two Interprocess Data Channel blocks that connect the two referenced models and help you to define the two-way interprocessor data channel between the two cores - TriCore0 and PPU.

TriCore0 referenced model (tc4x_IpcTC0.slx) has a discrete rate of 500 milliseconds. The IPCPPU referenced model (tc4x_IpcPPU.slx) is triggered by the IPCEvent, which is defined using the Hardware Mapping tool by navigating to Hardware > Hardware Mapping in the Simulink toolstrip..

The PPU referenced model uses a function-call subsystem that uses CRL (What Is Code Replacement? (Embedded Coder)) functionality to replace parts of generated code with hardware-specific code.

This example model uses two LEDs on the Infineon AURIX TC4xx board to help you verify data communication between the participating cores:

  • Port 13, Pin 0 for Digital Port Write block of TriCore0

  • Port 33, Pin 0 for Digital Port Write1 block of TriCore0

You define these pins using the Hardware Mapping tool, as shown in these two figures.

This configuration of peripherals ensures that the following data flow is implemented using LEDs upon deployment of the model on the board:

  • LED Port 33-Pin 0 blinks when data is sent from TriCore0 to PPU using the Interprocess Data Channel block available at the top part of the model.

  • LED Port 13-Pin 0 blinks with an offset of 1 sample when data is sent from PPU to TriCore0 using the Interprocess Data Channel1 block available at the bottom part of the model. The generated code from PPU is configured to apply a code replacement library (CRL) during code generation.

Define Configuration Parameters for TriCore0 and Analyze the Model

1. Open the TriCore0 referenced tc4x_IpcTC0 model.

2. Press Ctrl+E or click Modeling > Model Settings to open Configuration Parameters dialog box.

3. Select the Hardware Implementation pane and ensure that the following parameters are set to define the communication between TriCore0 and PPU.

The input data transferred to TriCore0 is a 1 X 2 vector of type uint16.

Define Configuration Parameters for PPU and Analyze the Model

1. Open the PPU referenced tc4x_IpcPPU model.

2. Press Ctrl+E or click Modeling > Model Settings to open Configuration Parameters dialog box.

3. Select the Hardware Implementation pane and ensure that the Processing Unit is set correctly.

Open the CRL subsystem in the model. Observe that the output_offset signal determines the offset added to the data received from TriCore0, and the result is sent back to TriCore0.

The CRL subsystem is added to demonstrate the CRL capabilities.

Generate Code and Deploy Model on Target Hardware

1. Click Configure, Build, Deploy & Start on the Hardware tab to launch the SoC Builder tool.

2. In the SoC Builder, prepare the model by first specifying the folder to use for project generation. Click Next.

3. In the Review Hardware Mapping section, click View/Edit to confirm the Hardware Mapping. Click Next.

4. In the Validate Model section, click Validate to check the model against the selected board (Infineon AURIX TC4x - Triboards).

If the message - Model validation successfully finished - appears, click Next.

5. In the next section of Soc Builder, Build Model, click Build. This process generates the binary executable. Click Next after the build is successful.

6. Connect the hardware (Infineon AURIX Tc4x board) to the host computer.

7. In the Soc Builder screen, click Load and Run. This action loads the generated binary to the connected board, programs the processor, and runs the application. Click Finish to close the Soc Builder.

8. You can observe the code generation report that contains code to model traceability or vice versa.

The code generation for the PPU reference model looks like this with the CRL applied.

9. Download and install the One Eye tool from Infineon to monitor signals from the hardware. Before using the One Eye tool, ensure that you download and install the latest version of the DAS tool.

10. Open the One Eye tool. Load the One Eye configuration file tc4x_IpcTopModel. OneEye file shipped with this example by clicking File > Load Configuration in the One Eye tool. Load the generated tc4x_IpcTopModel_sw_TriCore0.elf file by clicking Load ELF file in Debug box viewer. Reset the hardware and check the DAS connection status to monitor the signals.



Model compilation issue during validation of model.


When user clicks validate, SoC Builder window shows model compilation error. This issue occurs when there is a PPU core.

To resolve the issue, run the following command on the MATLAB® command prompt:


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