Clocked Set-Dominant SR-Latch

This example shows how to model a Set-dominant SR-Latch from Simscape™ Electrical™ logic components. Initial conditions are passed to the relevant AND gates via the initialization commands of the switches.

Model

Simulation Results from Simscape Logging

The plots below show the inputs and outputs for the Set-Dominant SR-Latch. Both inputs to the SR-Latch are set high, so its output state is set high for Q, and low for ~Q.