DUT Clock Frequency and Sample Rate

R2026b

Since R2026b

When you deploy a custom algorithm on an NI™ USRP™ radio, the DUT runs on an FPGA clock derived from the radio hardware. Three configuration parameters in the Configure HDL Code Generation Settings step control the clock frequency and data rate at the DUT boundary:

• Sample Rate — determines which master clock rate (MCR) the radio uses and, for the radio clock source, the DUT clock frequency.

• DUT Clock Source — selects whether the DUT is clocked by the radio clock (at the MCR) or by an independent custom clock.

• Target Frequency — the clock frequency used for DUT synthesis. When DUT Clock Source is set to Radio, this value is fixed at the maximum supported MCR for the device. When DUT Clock Source is set to Custom, you set this value to specify the custom DUT clock frequency.

This topic explains how the targeting workflow selects the MCR from the sample rate, how each clock source option affects DUT clock frequency and data arrival, and what to design for in each case.

For information about how Wireless Testbench™ application objects set the baseband sample rate, see Baseband Sample Rate in NI USRP Radios.

Sample Rate and MCR Selection

Each NI USRP radio supports a set of MCRs. The targeting workflow derives the baseband sample rate by dividing the MCR by an integer decimation or interpolation factor.

When Sample Rate is not equal to an MCR value, the software selects the lowest MCR that produces a valid integer factor for the specified rate. For example, on a USRP N310 radio with Sample Rate set to 960 kHz, the software selects MCR = 122.88 MHz and uses an integer factor of 128, rather than 153.6 MHz and an integer factor of 160.

To verify the selected MCR after deployment, read the DUTClockFrequency property on the usrp System object™. When DUT Clock Source is set to Radio, this value equals the MCR.

This table shows the supported MCRs and valid decimation or interpolation factors for each radio device.

Radio Device	MCR	Supported Decimation or Interpolation Factor
USRP E320	Using one transmit channel, one receive channel, or both: 40.00 MHz 50.00 MHz 61.44 MHz Using two transmit or receive channels: 20.00 MHz 25.00 MHz 30.72 MHz	1
		2
		3
		Even integer in the range from 4 to 256
		Multiple of 4 in the range from 256 to 512
		Multiple of 8 in the range from 512 to 1008
USRP N310	122.88 MHz 125.00 MHz 153.60 MHz	1
		2
		3
		Even integer in the range from 4 to 256
		Multiple of 4 in the range from 256 to 512
		Multiple of 8 in the range from 512 to 1016
USRP N320 USRP N321	200.00 MHz 245.76 MHz 250.00 MHz	1
		2
		3
		Even integer in the range from 4 to 256
		Multiple of 4 in the range from 256 to 512
		Multiple of 8 in the range from 512 to 1016
USRP X310	184.32 MHz 200.00 MHz	Integer in the range from 1 to 128
		Even integer in the range from 128 to 256
		Multiple of 4 in the range from 256 to 512
		Multiple of 8 in the range from 512 to 1016
USRP X410	245.76 MHz 250.00 MHz	1
		2
		3
		Even integer in the range from 4 to 256
		Multiple of 4 in the range from 256 to 512

For additional device capabilities such as supported center frequencies, number of channels, and gain ranges, see Determine Radio Device Capabilities.

Radio Clock Source

When DUT Clock Source is set to Radio (default), the DUT is clocked at the full MCR, regardless of the requested sample rate.

Data Arrival

The reference design includes digital down-conversion (DDC) and digital up-conversion (DUC) blocks between the radio front end and the DUT when either of these conditions is true:

• Sample Rate is set to a non-MCR value.

• Reference Design Optimization is set to None. The reference design includes the DDC and DUC blocks to maintain flexibility to use a derived sample rate at run time.

When Sample Rate is set to an MCR value and Reference Design Optimization is set to Moderate, High, or Maximum, the reference design does not include the DDC and DUC blocks.

When DDC and DUC blocks are present, they perform decimation or interpolation so the DUT processes data at the requested sample rate. The valid signal is asserted on clock cycles that contain new data. When DDC and DUC blocks are not present, data arrives on every DUT clock cycle. For more information about the reference design optimization settings, see Configure HDL Code Generation Settings.

Design Considerations

When you use the radio clock as the DUT clock source:

• Design for the highest MCR value supported by your device. The targeting workflow synthesizes the DUT at this value regardless of the sample rate you specify, so that the DUT meets timing at any MCR the radio might use.

• Enable processing logic only when the valid signal is asserted. When the sample rate is less than the MCR, data is not present on every clock cycle.

Custom DUT Clock Source

When DUT Clock Source is set to Custom, the DUT is clocked at the frequency specified by the Target Frequency parameter. The software generates a custom clock for the DUT using the Vivado^® Clocking Wizard and adds FIFOs for handling the clock domain crossing.

Data Arrival

As with the radio clock source, the reference design includes DDC and DUC blocks when Sample Rate is set to a non-MCR value or Reference Design Optimization is set to None. These blocks run in the radio clock domain and deliver data to the FIFO at the sample rate.

The FIFO delivers data to the DUT at the sample rate. Because the custom clock and radio clock are independent, the two clocks drift relative to each other over time. If the custom clock frequency is lower than or approximately equal to the sample rate, the DUT cannot consume data fast enough and the stream buffer overflows.

Design Considerations

When you use a custom clock as the DUT clock source:

• Set Target Frequency higher than the sample rate to prevent overflow caused by clock drift.

• Account for the additional FPGA resources consumed by the clock IP and FIFO buffers.

Choosing a custom clock source enables you to synthesize the DUT at a lower frequency, which relaxes timing constraints. For more information, see Reduce Resource Utilization and Achieve Timing Closure.

The valid range depends on the radio.

Radio Device	Minimum DUT Clock Frequency	Maximum DUT Clock Frequency
USRP E320	6.25 MHz	741 MHz
USRP N310, N320, N321, or X310	4.69 MHz	709 MHz
USRP X410	6.25 MHz	667 MHz