Issue Connecting to Xilinx FPGA Board for Simulation (Windows ,ZYNQ) Error:Did not receive version information from the hardware.

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I was trying to connect to my Xilinx ZYNQ FPGA board using MATLAB to run an FPGA-in-the-loop simulation, and I keep getting an error message. This error occurs in the validation Test when I usng the New FPGA Board Wizard.
Here is the result:
To stop the test, press "Ctrl+C" in the MATLAB console window.
Starting FPGA-in-the-Loop test ...
Generating FPGA programming file ...Passed
Programming FPGA ...Passed
Running FIL simulation ...Failed
Error:Did not receive version information from the hardware. You must have a valid connection, a compatible development board, and compatible versions of the block and FPGA programming file.
Here are the screenshots:
I've tried looking at all the other MATLAB forum posts for this issue, The URL of the most relevant question I found is :Issue Connecting to Xilinx FPGA Board for Simulation - MATLAB Answers - MATLAB Central (
Thanks to Max and YP's discussion, I finally had a clue to solve the problem. But it seems that this way does not solve the problem I am experiencing.
Here's what I've tried:
  • Change the number of the JTAG Chain Position, but it turns out that only 2 can load the bitstream properly.
  • Since the Reset pin is an optional setting, I chose not to set its information. But it didn't work
  • Lowering the JTAG Clock Frequency from the default 66MHz, although I've lowered it to 1MHz, has no effect
  • Compare the BSDL information in (Downloads (, but I didn't find anything to change here. This is because the default User 1-4 instructions in the New FPGA Board Wizard are the same as those provided in xc7z020_clg400.bsd. This proves them right.
  • Tried the fix file provided by YP in problem (Issue Connecting to Xilinx FPGA Board for Simulation - MATLAB Answers - MATLAB Central (, again did not solve my problem.
Here is my Version Information: Windows 10, Vivado 2018.3, Matlab R2021a
And the Information of my hardware:
  • Digilent(R) JTAG HS2 cable.
  • The schematic of the development board's backboard and core board is in the attachment, and I also took a photo of the hardware. I can post it because it's a public resource on the web.
I would be very grateful and again if anyone could provide some help!

Accepted Answer

YP on 5 Jun 2023
Edited: YP on 6 Jun 2023
As mentioned on this help doc.
If you are using a Zynq device, and it is the only item in the device chain, enter 4 in Sum of IR length before and 0 in Sum of IR length after.
壹 王
壹 王 on 6 Jun 2023
Edited: 壹 王 on 6 Jun 2023
Thank you very much for your reply. It has been very helpful to me and my problem has been resolved!
The webpage you provided cannot be opened, perhaps because it is not a officially released software manual and therefore cannot be accessed by the outside world. But I found the corresponding manual for R2021b version by referring to the path:FPGA Board Editor - MATLAB & Simulink - MathWorks 中国
Once again, I would like to express my gratitude to you and wish you good health and all the best!
The following is my settings interface for future readers to refer to:

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