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sai kumar morla
sai kumar morla on 5 May 2017
Commented: Jiaqi Xu on 8 Mar 2024
Hello Matlab community,
For Fpga in loop with a simulink model i tried fpga custom board manager , I tried to validate the board design but following error has occured please I could not understand what its meaning and help me in this regard
"To stop the test, press "Ctrl+C" in the MATLAB console window.
Starting FPGA-in-the-Loop test ...
Generating FPGA programming file ...Passed
Programming FPGA ...Passed
Checking Ethernet connection ...Passed
Running FIL simulation ...Failed
Error:Did not receive version information from the hardware. You must have a valid connection, a compatible development board, and compatible versions of the block and FPGA programming file.
I have used xilinx partner digilent board genesys 2 board with chip KINTEX 7 325TFF900 which is similar to KC705 board please help me in this as it required for my research.
Thank you in advance,
With regards,
Sai kumar

Answers (1)

Tao Jia
Tao Jia on 5 May 2017
Edited: Walter Roberson on 14 Jun 2017
Hi Sai,
The Genesys 2 board is actually quite different from KC705:
  1. KC705 uses a Marvell Ethernet PHY chip, while Genesys uses Realtek RTL8211E-VL PHY. Different PHY chip might need special configuration to make it work
  2. KC705 uses GMII interface between FPGA and Ethernet PHY chip, while Genesys uses RGMII. Those are two totally different interface.
Given above difference, I would recommend you to try the JTAG communication interface instead of Ethernet.
Hope this helps,
Tao Jia
Tao Jia on 14 Jun 2017
Hi Sai,
I would suspect this is related to the clocking. If you don't have a working clock or rest stuck at active, you might get error like this. If would be helpful if you can post your customization file here.
Jiaqi Xu
Jiaqi Xu on 8 Mar 2024
Hi Sai and Tao,
Currently, I am using the same board (Genesys2) and meeting the same issue. May I ask have you solved this issue already? I would appreciate any potential help from your side.
Thanks again,

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