General CRC Syndrome Detector HDL Optimized
Detect errors in input data using CRC
Libraries:
Communications Toolbox HDL Support /
Error Detection and Correction /
CRC
Description
The General CRC Syndrome Detector HDL Optimized block performs a cyclic redundancy check (CRC) on data and compares the resulting checksum with the appended checksum. The General CRC Syndrome Detector HDL Optimized block processing is optimized for HDL code generation. If the two checksums do not match, the block reports an error. Instead of processing an entire frame at once, the block accepts and returns a data sample stream with accompanying control signals. The control signals indicate the validity of the samples and the boundaries of the frame. To achieve higher throughput, the block accepts vector data up to the CRC length and implements a parallel architecture.
Examples
Ports
Input
dataIn — Input data
scalar  vector
Input data, specified as one of these options.
Scalar – Specify an integer representing several bits. For this case, the block supports an unsigned integer (
uint8
,uint16
, oruint32
) orfixdt(0,N,0)
data type.Vector – Specify a vector of binary values. For this case, the block supports a
double
orBoolean
data type.
The data width must be less than or equal to the CRC length, and the CRC length must be divisible by the data width. For CRCCCITT/CRC16, the valid data widths are 16, 8, 4, 2, and 1.
Example: The uint8
vector input [0 0 0 1 0 0 1
1]
is equivalent to 19
.
Data Types: double
 uint8
 uint16
 uint32
 fixed point
 Boolean
startIn — Start of input frame indicator
scalar
Start of input frame indicator, specified as a Boolean scalar.
Data Types: Boolean
endIn — End of input frame indicator
scalar
End of input frame indicator, specified as a Boolean scalar.
Data Types: Boolean
validIn — Valid input data indicator
scalar
Valid input data indicator, specified as a Boolean scalar.
This a control signal that indicates if the data on the dataIn port is valid.
Data Types: Boolean
Output
dataOut — Output data
scalar  vector
Output data, returned as a scalar or vector. The output data type and size are the same as the input data.
Data Types: double
 uint8
 uint16
 uint32
 Boolean
 fixed point
startOut — Start of output frame indicator
scalar
Start of output frame indicator, returned as a Boolean scalar.
Data Types: Boolean
endOut — End of output frame indicator
scalar
End of output frame indicator, returned as a Boolean
scalar.
Data Types: Boolean
validOut — Valid output data indicator
scalar
Valid output data indicator, returned as a Boolean scalar.
This is a control signal that indicates if the data on the dataOut port is valid.
Data Types: Boolean
err — Error indicator
scalar
Error indicator for the corruption of the received data, returned as a Boolean scalar.
When this value is 1
, the message contains at least one error.
When this value is 0
, the message contains zero errors.
Data Types: Boolean
Parameters
Polynomial — Generator polynomial
[1 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 1]
(default)  binary vector
Specify the generator polynomial as a binary vector with coefficients in descending order of powers. The vector length is equal to the degree of the polynomial plus 1.
Initial state — Initial conditions of shift register
0
(default)  binary scalar  binary vector
Specify initial conditions of the internal shift register as a binary, doubleprecision, or singleprecision scalar or vector. For vector inputs, the length of the initial state must be equal to the degree of the generator polynomial.
Direct method — Method of calculating checksum
off
(default)  on
Specify the method of calculating checksum as a Boolean scalar.
Select this parameter to use the direct algorithm for CRC checksum calculations.
Clear this parameter to use the nondirect algorithm for CRC checksum calculations.
To learn about the direct and nondirect algorithms, see Cyclic Redundancy Check Codes.
Reflect input — Input byte order
off
(default)  on
Specify the input byte order.
Select this parameter for the block to flip each input byte before it enters the shift register.
Clear this parameter for the block to pass the message data to the shift register unchanged.
The input data width must be a multiple of 8.
Reflect CRC checksum — Checksum byte order
off
(default)  on
Specify the checksum byte order.
Select this parameter for the block to flip each checksum byte before passing it to the final XOR stage.
Clear this parameter for the block to pass the checksum byte to the final XOR stage unchanged.
The input data width must be a multiple of 8.
Final XOR value — Checksum
0
(default)  binary scalar  binary vector
Specify the checksum as a binary, doubleprecision, or singleprecision data type scalar or vector. The block performs XOR operation on the CRC checksum with this value before appending it to the input data.
If you specify a vector input, the vector length must be equal to the degree of the generator polynomial.
Algorithms
When you use vector or integer input, the block implements a parallel CRC algorithm [1].
To provide high throughput for modern communications systems, the block implements the CRC algorithm with a parallel architecture. This architecture recursively calculates M bits of a CRC checksum for each W input bits. At the end of the frame, the final checksum result is appended to the message. For a polynomial length of M, the recursive checksum calculation for W bits in parallel is
$${X}^{\text{'}}={F}_{W}(\times )X(+)D.$$
F_{W} is an MbyM matrix that selects elements of the current state for the polynomial calculation with the new input bits. D is an Melement vector that provides the new input bits, ordered in relation to the generator polynomial and padded with zeros. The block implements the (×) with logical AND and (+) with logical XOR.
Timing Diagram
This waveform shows streaming data and the accompanying control signals for a CRC16 with 8bit binary vector input. The input frames are contiguous. The output frames include space between them because the detector block removes the checksum word.
This waveform diagram shows continuous input data. Noncontinuous data is also supported.
Initial Delay
The General CRC Syndrome Detector HDL Optimized block introduces a latency on the output. This latency can be computed with the following equation, assuming the input data is continuous:
initialdelay = 3 * (CRC length/input data width) + 2.
Performance
The performance of the synthesized HDL code varies with your target and synthesis options. The generated HDL code is targeted to the Xilinx^{®} Zynq^{®} 7000 SoC ZC706 Evaluation Kit.
This table shows the resource and performance data synthesis results for a 16by1
Boolean
vector input, when you set the Polynomial
parameter to [ 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1 ]
and
enable the Direct method parameter.
Slice LUTs  Slice Registers  Block RAM  Clock Frequency (MHz) 

124  162  0  718.67 
This table shows the resource and performance data synthesis results for a
ufix1
scalar input, when you set the Polynomial
parameter to [ 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1 ]
and
enable the Direct method parameter.
Slice LUTs  Slice Registers  Block RAM  Clock Frequency (MHz) 

159  206  0  685.66 
References
[1] Campobello, G., G. Patane, and M. Russo. “Parallel Crc Realization.” IEEE Transactions on Computers 52, no. 10 (October 2003): 1312–19. https://doi.org/10.1109/TC.2003.1234528.
Extended Capabilities
C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.
Not recommended for production code.
HDL Code Generation
Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.
HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.
This block has one default HDL architecture.
ConstrainedOutputPipeline  Number of registers to place at
the outputs by moving existing delays within your design. Distributed
pipelining does not redistribute these registers. The default is

InputPipeline  Number of input pipeline stages
to insert in the generated code. Distributed pipelining and constrained
output pipelining can move these registers. The default is

OutputPipeline  Number of output pipeline stages
to insert in the generated code. Distributed pipelining and constrained
output pipelining can move these registers. The default is

Version History
Introduced in R2012b
MATLAB Command
You clicked a link that corresponds to this MATLAB command:
Run the command by entering it in the MATLAB Command Window. Web browsers do not support MATLAB commands.
Select a Web Site
Choose a web site to get translated content where available and see local events and offers. Based on your location, we recommend that you select: .
You can also select a web site from the following list:
How to Get Best Site Performance
Select the China site (in Chinese or English) for best site performance. Other MathWorks country sites are not optimized for visits from your location.
Americas
 América Latina (Español)
 Canada (English)
 United States (English)
Europe
 Belgium (English)
 Denmark (English)
 Deutschland (Deutsch)
 España (Español)
 Finland (English)
 France (Français)
 Ireland (English)
 Italia (Italiano)
 Luxembourg (English)
 Netherlands (English)
 Norway (English)
 Österreich (Deutsch)
 Portugal (English)
 Sweden (English)
 Switzerland
 United Kingdom (English)