Checks property values in reference design object
validateReferenceDesignForDeepLearning checks that the
hdlcoder.ReferenceDesign object is compatible with the deep learning
processor IP core generation workflow.
Reference Design Requirements
validateReferenceDesign method checks your
hdlcoder.ReferenceDesign object for these requirements:
Your reference design must have an AXI4 Slave interface. You use this interface to access registers in the deep learning processor IP core.
Your reference design must have three AXI4 Master interfaces with
"AXI4 Master Activation Data",
"AXI4 Master Weight Data", and
"AXI4 Master Debug". The deep learning processor IP core uses these AXI4 Master interfaces to access memory for network storage and intermediate calculations.
Your reference design must have a registered memory address space. Use the
registerDeepLearningMemoryAddressSpaceto register a memory address space. To run a variety of deep learning networks on your deep learning processor IP core, it is recommended to register a minimum of 512 MB of memory address space.
Register a target interface for your reference design by using the
registerDeepLearningTargetInterface method. You can use the registered
target interface to run your deep learning network on the generated deep learning processor IP
core by using MATLAB® and a
Introduced in R2021b