Critical Path Estimation
R2026bCritical path is the combinational path between an input and output that has the maximum timing delay. To quickly identify the most likely critical path in your design, use critical path estimation. Critical path estimation speeds up this iterative process of finding the critical path. It optimizes the critical path until your design timing meets the target frequency that you want.
Functions
genhdltdb | Generate timing databases for specified target device, device speed grade, and synthesis tool |
Model Settings
| Enable-based constraints | Enable multiple clock cycles for data to propagate between registers |
| Generate high-level timing critical path report | Insert highlighting script that maps estimated critical path in code generation report |
| Custom Timing Database Directory | Path to custom timing files |
Classes
hdlcoder.TimingGenerator | Base class to implement custom tool and device support for critical path estimation reporting (Since R2024a) |
Topics
- Critical Path Estimation Without Running Synthesis
Find the estimated critical paths in your design without using third-party synthesis tools.
- Enable-Based Multicycle Path Constraints
Generate enable-based constraints for synthesis tools to meet timing requirements of multicycle paths in single clock mode.
- Generate Custom Timing Database for Custom Tools and Devices
Create a custom timing generator to characterize custom devices for your custom tools.
- Distributed Pipelining Using Synthesis Timing Estimates
Use synthesis timing estimates for distributed pipelining to more accurately reflect how components function on hardware to better distribute pipelines and increase clock frequency for your target device.
- Generate Multicycle Path Constraints for Multirate Models
Generate Multicycle Path Constraints for Different Rates and Phases.
- Choose Between Multicycle Path Constraints and Clock-Rate Pipelining
Decide whether to use multicycle path constraints (MCP) or clock-rate pipelining (CRP) to meet timing requirement.
Featured Examples
Use Multicycle Path Constraints to Meet Timing for Slow Paths
Apply multicycle path constraints in your design to meet timing requirements. Using multicycle path constraints can save area and reduce synthesis run times. For more information, see Enable-Based Multicycle Path Constraints.
Iteratively Meet Timing Requirements Using Multicycle Path Constraints for Cadence Genus
Use multicycle path constraints with HDL Workflow Advisor and Cadence® Genus synthesis tools to meet the timing requirements for ASIC devices.
