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Speed Optimization

Critical path estimation and reduction, pipeline register insertion, loop unrolling, and automated iterative clock frequency optimization

Improve the timing and increase the clock speed of your design for a target FPGA or SoC device by reducing the critical path. You can reduce the critical path by using different pipelining methods. For an overview on speed optimizations, see Speed and Area Optimizations in HDL Coder.


hdlcoder.optimizeDesignAutomatic iterative HDL design optimization
hdlcoder.supportedDevicesShow supported target hardware and device details


hdlcoder.OptimizationConfighdlcoder.optimizeDesign configuration object


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Deserializer1DConvert scalar stream or smaller vectors to vector signal
Multiply-AccumulatePerform a multiply-accumulate operation on the inputs
Multiply-AddMultiply-add combined operation
Serializer1DConvert vector signal to scalar or smaller vectors



Resolve Simulation Mismatch when Pipelining with a Feedback Loop Outside the DUT

Learn how to resolve simulation mismatch issues when using pipeline optimizations with feedback loops.