addRegisterInterface

R2026b

Write data to IP core or read data from IP core using AXI4 or AXI4-Lite interface

Syntax

addRegisterInterface(hFPGA)

addRegisterInterface(hFPGA, Name=Value)

Description

addRegisterInterface(hFPGA) adds a register interface that you can use to control the DUT ports mapped to AXI4 or AXI4-Lite interfaces in the HDL Coder™ generated IP core from MATLAB^®.

addRegisterInterface(hFPGA, Name=Value) adds a register interface that you can use to control the DUT ports mapped to AXI4 or AXI4-Lite interfaces in the HDL Coder generated IP core from MATLAB, with one or more name-value arguments.

Examples

Add Register Interface for Xilinx Target

Add register interface for a Xilinx^® target.

Create a target object, hFPGA, for the target device.

hFPGA = fpga("Xilinx")

hFPGA = 

  fpga with properties:

       Vendor: "Xilinx"
   Interfaces: [0x0 fpgaio.interface.InterfaceBase]

    

Add the AXI4 register interface to the hFPGA object by using the addRegisterInterface function.

%% AXI4-Lite
addRegisterInterface(hFPGA, ...
	... % Interface properties
    InterfaceID="AXI4-Lite", ...
    BaseAddress=0xA0000000, ...
    AddressRange=0x10000, ...
    ... % Driver properties
    WriteDeviceName="mwipcore0:mmwr0", ...
    ReadDeviceName="mwipcore0:mmrd0");

After you have added the interfaces, use the mapPort function to map the ports to that interface, and then read and write data. See Map DUT Ports in HDL IP Core to Register Interfaces.

Add Register Interface for Intel Target

Add register interface for an Intel^® target.

Create a target object, hFPGA, for an Intel target.

hFPGA = fpga("Intel")

hFPGA = 

  fpga with properties:

       Vendor: "Intel"
   Interfaces: [0x0 fpgaio.interface.InterfaceBase]

    

Add the AXI4 register interface to the hFPGA object by using the addRegisterInterface function.

%% AXI4
addRegisterInterface(hFPGA, ...
	... % Interface properties
    InterfaceID="AXI4", ...
    BaseAddress=0xA0000000, ...
    AddressRange=0x10000, ...
    ... % Driver properties
    WriteDeviceName="mwipcore0:mmwr0", ...
    ReadDeviceName="mwipcore0:mmrd0");

After you have added the interfaces, use the mapPort function to map the ports to that interface, and then read and write data. See Map DUT Ports in HDL IP Core to Register Interfaces.

Add Register Interface for JTAG-Connected FPGA

Add a register interface for a Xilinx or Intel FPGA or SoC device connected through a JTAG interface.

Create a JTAG connection object, jtagObj, for the target device.

jtagObj = jtagchain("AMD");

Create an FPGA hardware object, hFPGA, by using the JTAG connection object.

hFPGA = fpga(jtagObj)

hFPGA = 

  fpga with properties:

       Vendor: "AMD"
   Interfaces: [0x0 fpgaio.interface.InterfaceBase]

    

Add the AXI4-Lite register interface to the hFPGA object by using the addRegisterInterface function.

addRegisterInterface(hFPGA, ...
    ... % Interface properties
    InterfaceID="AXI4-Lite", ...
    BaseAddress=0xA0000000, ...
    AddressRange=0x10000, ...
    DriverAddressMode="Full");

After you add the interface, use the mapPort function to map DUT ports to the interface and then use the readPort and writePort functions to access registers. See Map DUT Ports in HDL IP Core to Register Interfaces.

Input Arguments

hFPGA — Target FPGA object

fpga object

fpga object for the target vendor, specified as an fpga object.

Name-Value Arguments

Specify optional pairs of arguments as Name1=Value1,...,NameN=ValueN, where Name is the argument name and Value is the corresponding value. Name-value arguments must appear after other arguments, but the order of the pairs does not matter.

Example: addRegisterInterface(hFPGA,InterfaceID="AXI4-Lite") creates a register interface with InterfaceID as AXI4-Lite.

InterfaceID — Name of register interface

"AXI4-Lite" | "AXI4" | string

Name of AXI4-Lite or AXI4 interface that you want to map the DUT ports to, specified as a string.

BaseAddress — Base address

0x0 (default) | numeric value

Base address for AXI4 or AXI4-Lite register interface, specified as a numeric value.

Example: 0x40010000

AddressRange — Address range

numeric value

Address range for AXI4 or AXI4-Lite interface, specified as a numeric value.

Example: 0x10000

WriteDeviceName — IIO device name to write data

"mwipcore0:mmwr0" (default) | string array

Name and path of the IIO device that you want to write to. When you generate the IP core by using the IP Core Generation workflow, the default name is mwipcore0:mmwr0.

Example: "mwipcore0:mmwr0"

ReadDeviceName — IIO device name to read data

"mwipcore0:mmrd0" (default) | string array

Name and path of the IIO device that you want to read from. When you generate the IP core by using the IP Core Generation workflow, the default name is mwipcore0:mmrd0.

Example: "mwipcore0:mmrd0"

WriteDriver — Name of AXI driver to perform write operation

driver object

Name of the AXI driver to perform the write operation, specified as a driver object. For standalone FPGA boards, you can specify this property as the aximanager object. For SoC platforms, addRegisterInterface creates the drivers automatically.

When the FPGA hardware object is created from a jtagchain object, addRegisterInterface automatically configures the JTAG AXI driver and you do not need to specify this argument.

Example: aximanager("Xilinx")

ReadDriver — Name of AXI driver to perform read operation

driver object

Name of the AXI driver to perform the read operation, specified as a driver object. For standalone FPGA boards that do not have an embedded ARM^® processor, you can specify this property as the aximanager object. For SoC platforms, addRegisterInterface creates the drivers automatically.

When the FPGA hardware object is created from a jtagchain object,addRegisterInterface automatically configures the JTAG AXI driver and you do not need to specify this argument.

Example: aximanager("Xilinx")

DriverAddressMode — AXI driver to perform read operation

"Offset" (default) | "Full"

Specify whether the AXI driver expects a full address that includes the base address and the offset address, or whether it expects only an offset address.

Example: "Offset"

Version History

Introduced in R2020b

R2026a: Renamed AXI4-Slave elements in HDL Coder

HDL Coder has renamed several function names and user interface elements that previously used the term “slave”. These changes reflect the adoption of inclusive terminology in MathWorks software and documentation.

Functionality Type	Name in Previous Releases	Current Name
Function	addAXI4SlaveInterface	addRegisterInterface
Method	hdlcoder.ReferenceDesign.addAXI4SlaveInterface	hdlcoder.ReferenceDesign.addRegisterInterface