HDL Coder™ provides configuration options that affect HDL implementation and synthesized
logic.
| Block Parameter Setting | Description |
|---|
Set External reset to
Level. | Generates a reset port in the HDL code. |
| Select Show enable port. | Generates an enable port in the HDL code. |
For Initial condition, set Source to
Dialog and enter the value. | Specifies an initial condition for the block. |
Set Input processing to Columns as channels
(frame based) or Elements as channels (sample
based). | Expects vector input data, where each element of the vector represents a sample
in time. |
Additional Settings When Using State Control BlockIf you use a State Control block with the Delay block
inside a subsystem in your Simulink model, use these additional settings.
| Block Parameter Setting | Description |
|---|
Set External reset to Level
hold for Synchronous mode and
Level for Classic mode of
the State Control block. | Generates a reset port in the HDL code. |
| Set Delay length to zero for a Delay
block with an external enable port. | Treated as a wire in only Synchronous mode of the
State Control block. |
| Set Delay length to zero for a Delay
block with an external reset port. | Treated as a wire in Synchronous and
Classic modes of the State Control
block. |
For more information about the State Control block, see State Control.
HDL ArchitectureThis block has one default HDL architecture.
HDL Block Properties| AllowDelayDistribution | Allow delay to be distributed or absorbed during the distributed
pipelining and delay absorption optimizations. The default is
inherit. For more details, see AllowDelayDistribution. |
| InputPipeline | Number of input pipeline stages
to insert in the generated code. Distributed pipelining and constrained
output pipelining can move these registers. The default is
0. For more details, see InputPipeline.
|
| OutputPipeline | Number of output pipeline stages
to insert in the generated code. Distributed pipelining and constrained
output pipelining can move these registers. The default is
0. For more details, see OutputPipeline.
|
| ResetType | Suppress reset logic generation. The default is default,
which generates reset logic. See also ResetType.
|
| UseRAM | Map delays to RAM instead of registers. The default is off.
See also UseRAM.
|
Variable Integer Delay SupportYou can generate HDL code for the Delay block that has set through the Input port. Input
delay length can be integer types or floating-point types.
The code generation supports positive integer values at the 'd' port of the delay
block. The delay length set through the input port must be between
0 and Upper limit, specified in the Block
Parameters dialog box.
For negative delay length values, HDL Coder translates these negative delay length to 0.
Similarly, if you specify delay length greater than the upper limit, HDL Coder translates the delay length to the Upper limit value.
Upper limit range is defined by the range of the delay length input data type. For
example, if you specify delay length input data type as uint8, then
the upper limit must not exceed 255.
You can use enable and reset ports for the variable integer Delay block.
Complex Data SupportThis block supports code generation for complex signals.
Restrictions
For Initial condition, Source set to
Input port is not supported for HDL code
generation.
HDL code generation supports only the Boolean data type at the Reset and Enable
ports.
HDL Block Property UseRAM for RAM mapping is not supported
for Delay block that has set through the
Input port.
The Delay block that has set through the
Input port does not support bus and matrix data input
for HDL code generation.
