addAXI4MasterInterface

R2026b

Class: hdlcoder.ReferenceDesign
Namespace: hdlcoder

Add and define AXI4 Master interface

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Syntax

addAXI4MasterInterface(InterfaceConnection=Interface_Connection)
addAXI4MasterInterface(InterfaceConnection=Interface_Connection,TargetAddressSegments=Target_Address_Segments)
addAXI4MasterInterface(InterfaceConnection=Interface_Connection,Name=Value)
addAXI4MasterInterface(InterfaceConnection=Interface_Connection,TargetAddressSegments=Target_Address_Segments,Name=Value)

Description

addAXI4MasterInterface(InterfaceConnection=Interface_Connection) adds and defines an AXI4 Master interface for an Intel® Qsys reference design.

addAXI4MasterInterface(InterfaceConnection=Interface_Connection,TargetAddressSegments=Target_Address_Segments) adds and defines an AXI4 Master interface for a Xilinx® Vivado® reference design.

addAXI4MasterInterface(InterfaceConnection=Interface_Connection,Name=Value) adds and defines an AXI4 Master interface for an Intel Qsys reference design, with additional options specified by one or more name-value arguments.

addAXI4MasterInterface(InterfaceConnection=Interface_Connection,TargetAddressSegments=Target_Address_Segments,Name=Value) adds and defines an AXI4 Master interface for a Xilinx Vivado reference design, with additional options specified by one or more name-value arguments.

Input Arguments

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Name of the reference design port that is connected to the AXI4 Master interface, specified as a character vector.

Example: 'axi_interconnect_1/S01_AXI'

Target address segment of the Xilinx Vivado reference design, specified as a character vector. The format of the target address segment is {'SegmentName', low address, range}. You must use a power of 2 value for range.

Example: {{'mig_7series_0/memmap/memaddr',hex2dec('40000000'),hex2dec('40000000')}}

Tip

To add more than one AXI4 Master interface to your reference design, call the addAXI4MasterInterface method multiple times depending on the number of interfaces you want to add. For each additional interface, specify a unique InterfaceID.

Name-Value Arguments

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Specify optional pairs of arguments as Name1=Value1,...,NameN=ValueN, where Name is the argument name and Value is the corresponding value. Name-value arguments must appear after other arguments, but the order of the pairs does not matter.

Name of the AXI4 Master interface that you add to the reference design, specified as a character vector or string. If you create multiple AXI4 Master interfaces, make sure that you use unique names for each interface.

Example: InterfaceID="AXI4 Master 1"

Specify whether you want the AXI4 Master interface to support a read channel, specified as a logical value.

Example: ReadSupport=true specifies support for an AXI4 Master read interface connection.

Specify whether you want the AXI4 Master interface to support a write channel, specified as a logical value.

Example: WriteSupport=true specifies support for an AXI4 Master write interface connection.

Maximum width for the Data signal that is transferred across the AXI4 Master interface, specified as an integer.

Example: MaxDataWidth=32 specifies maximum data width of 32 bits.

Width of the AXI4 Master interface read and write addresses, specified as an integer. The AddrWidth value controls the address width in the AXI4 Master interface within the HDL Coder™ generated IP core. It should match the address width of the AXI4 Slave interface in the reference design that you intend to connect to the AXI4 Master interface in the HDL Coder generated IP core.

Example: AddrWidth=32 specifies an address size of 32 bits.

Example: AddrWidth=64 specifies an address size of 64 bits. Use a larger address width when your IP core needs to access memory locations with base addresses beyond the 32-bit (4 GB) range, such as the LPDDR4 external memory on Xilinx Versal® device.

Default starting address of the AXI4 Master read interface, specified as an integer.

Example: DefaultReadBaseAddr=hex2dec("40000000") specifies hex2dec("40000000") as the starting read address.

Default starting address of the AXI4 Master write interface, specified as an integer.

Example: DefaultWriteBaseAddr=hex2dec("41000000") specifies hex2dec("41000000") as the starting write address.

Indicate if the AXI4 Master interface is connected to a memory region, specified as true or false. Set this value to true to enable device tree generation for the IP core AXI4 Master interfaces.

Example: HasMemoryConnection=true

Data Types: logical

Regions of memory accessible to the AXI4 Master interface and the processor, specified as a numeric array. Use these regions to exchange data with the AXI4 Master interface. Specify the memory region as an address in range tuple. If there are multiple accessible memory regions, specify an N-by-two matrix, where each row is an address in range tuple.

Example: ProcessorAccessibleMemoryRegion=[0x80000000 0x200000]

Example: ProcessorAccessibleMemoryRegion=[0x80000000 0x200000;0xA0000000 0x200000]

Reference to the processor-accessible memory regions in the registered device tree, specified as a character vector, string, string array, or a cell array of character vectors. Set the value to match the name of the corresponding memory region node in the registered device tree. The memory region node in the device tree should have the same address space as defined in the ProcessorAccessibleMemoryRegion. If there are multiple memory regions, specify a list of reference nodes. References to device tree nodes must start with "&". To reference a node by its label, specify "&" before the label. For example, "&myLabel". To reference a node by its path, specify the path inside "&{"and"}". For example, "&{/myNode/childNode}".

Example: DeviceTreeMemoryRegionNode="&plmem"

Example: DeviceTreeMemoryRegionNode=["&plmem","&sharedmem"]

Design fragment files to source into the generated Vivado project, specified as a cell array. Use this argument to add hardware components that are required only when the AXI4-Master interface is mapped, such as PL DDR memory controllers or DMA infrastructure.

Specify file names relative to the reference design plugin folder, as absolute paths, or relative to folders added by using addIncludeFolder. If the file is located in an added folder, you can specify only the file name.

This argument supports only Xilinx Vivado reference designs. The design fragment files must use the .tcl extension. The generated project sources the specified files after the base custom block design TCL file and includes them only when the AXI4-Master interface is mapped.

Example: DesignFragment={"shared\add_pl_ddr4.tcl"} specifies a file name relative to the reference design plugin folder.

Example: DesignFragment={"C:\work\tcl\add_pl_ddr4.tcl"} specifies an absolute file path.

Example: DesignFragment={"add_pl_ddr4.tcl"} specifies a file in a folder added by using addIncludeFolder.

Device tree fragment files to append to the generated Linux® device tree, specified a cell array. Use this argument to describe hardware resources that the processor accesses through the AXI4-Master interface, such as memory regions or DMA channels.

Specify file names relative to the reference design plugin folder, as absolute paths, or relative to folders added by using addIncludeFolder. If the file is located in an added folder, you can specify only the file name.

This argument supports only Xilinx Vivado reference designs. The device tree fragment files must use the .dts or .dtsi extension. The generated device tree appends the specified files and includes them only when the AXI4-Master interface is mapped.

Example: DeviceTreeFragment={"shared\devicetree_sharedmem_pl.dtsi"} specifies a file name relative to the reference design plugin folder.

Example: DeviceTreeFragment={"C:\work\devicetrees\devicetree_sharedmem_pl.dtsi"} specifies an absolute file path.

Example: DeviceTreeFragment={"devicetree_sharedmem_pl.dtsi"} specifies a file in a folder added by using addIncludeFolder.

Constraint files to add to the generated project, specified as a cell array. Use this argument to specify constraints associated with hardware introduced by the AXI4-Master interface, such as pin assignments, I/O standards, or timing exceptions.

Specify file names relative to the reference design plugin folder, as absolute paths, or relative to folders added by using addIncludeFolder. If the file is located in an added folder, you can specify only the file name.

This argument supports only Xilinx Vivado reference designs. The constraint files must use the .xdc extension. The generated project adds the specified files to the project constraint set and includes them only when the AXI4-Master interface is mapped.

Example: ConstraintFragment={"shared\constr.xdc"} specifies a file name relative to the reference design plugin folder.

Example: ConstraintFragment={"C:\work\constraints\constr.xdc"} specifies an absolute file path.

Example: ConstraintFragment={"constr.xdc"} specifies a file in a folder added by using addIncludeFolder.

Version History

Introduced in R2017b

See Also

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