Hold input data between samples
Specify how long subrate signal values are held in valid state
Model Configuration Pane: Test Bench
Description
Specify how long subrate signal values are held in valid state.
Dependencies
This option is disabled if you select the entire model. Select the DUT instead for Generate HDL for setting.
Settings
On
(default) | Off
On
Data values for subrate signals are held in a valid state across N base-rate clock cycles, where N is the number of base-rate clock cycles that elapse per subrate sample period. (N >= 2.)
Off
Data values for subrate signals are held in a valid state for only one base-rate clock cycle. For the subsequent base-rate cycles, data is in an unknown state (expressed as
'X'
) until leading edge of the next subrate sample period.
Tips
In most cases, the default (On) is the best setting for Hold input data between samples. This setting matches the behavior of a Simulink® simulation, in which subrate signals are held valid through each base-rate clock period.
In some cases (for example modeling memory or memory interfaces), it is desirable to clear Hold input data between samples. In this way you can obtain diagnostic information about when data is in an invalid ('X'
) state.
To set this property, use hdlset_param
or makehdltb
. To view the property value, use hdlget_param
.
For example, you can specify this parameter for the symmetric_fir
subsystem inside the sfir_fixed
model using either of these methods.
Pass the property as an argument to the
makehdltb
function.makehdltb('sfir_fixed/symmetric_fir', ... 'HoldInputDataBetweenSamples', 'off')
When you use
hdlset_param
, you can set the parameter on the model and then generate HDL code usingmakehdltb
.hdlset_param('sfir_fixed', 'HoldInputDataBetweenSamples', 'off') makehdltb('sfir_fixed/symmetric_fir')
Recommended Settings
No recommendations.
Programmatic Use
Parameter: HoldInputDataBetweenSamples |
Type: character vector |
Value: 'on' | 'off' |
Default: 'on' |
Version History
Introduced in R2012a