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makehdltb

Generate HDL test bench from model or subsystem

Description

example

makehdltb(dut) generates an HDL test bench from the specified subsystem or model reference.

Note

If you have not previously executed makehdl within the current MATLAB® session, makehdltb calls makehdl to generate model code before generating the test bench code. Properties passed in to makehdl persist after makehdl executes, and (unless explicitly overridden) are passed to subsequent makehdl calls during the same MATLAB session.

example

makehdltb(dut,Name,Value) generates an HDL test bench from the specified subsystem or model reference with options specified by one or more name-value pair arguments.

Examples

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Generate VHDL® DUT and test bench for a subsystem.

Use makehdl to generate VHDL code for the subsystem symmetric_fir.

makehdl('sfir_fixed/symmetric_fir')
### Generating HDL for 'sfir_fixed/symmetric_fir'.
### Starting HDL check.
### HDL check for 'sfir_fixed' complete with 0 errors, 0 warnings, 
    and 0 messages.
### Begin VHDL Code Generation for 'sfir_fixed'.
### Working on sfir_fixed/symmetric_fir as 
    hdlsrc\sfir_fixed\symmetric_fir.vhd
### HDL code generation complete.

After makehdl is complete, use makehdltb to generate a VHDL test bench for the same subsystem.

makehdltb('sfir_fixed/symmetric_fir')
### Begin TestBench generation.
### Generating HDL TestBench for 'sfir_fixed/symmetric_fir'.
### Begin simulation of the model 'gm_sfir_fixed'...
### Collecting data...
### Generating test bench: hdlsrc\sfir_fixed\symmetric_fir_tb.vhd
### Creating stimulus vectors...
### HDL TestBench generation complete.
The generated VHDL test bench code is saved in the hdlsrc folder.

Generate Verilog® DUT and test bench for a subsystem.

Use makehdl to generate Verilog code for the subsystem symmetric_fir.

makehdl('sfir_fixed/symmetric_fir','TargetLanguage','Verilog')
### Generating HDL for 'sfir_fixed/symmetric_fir'.
### Starting HDL check.
### HDL check for 'sfir_fixed' complete with 0 errors, 0 warnings, 
    and 0 messages.
### Begin Verilog Code Generation for 'sfir_fixed'.
### Working on sfir_fixed/symmetric_fir as 
    hdlsrc\sfir_fixed\symmetric_fir.v
### HDL code generation complete.

After makehdl is complete, use makehdltb to generate a Verilog test bench for the same subsystem.

makehdltb('sfir_fixed/symmetric_fir','TargetLanguage','Verilog')
### Begin TestBench generation.
### Generating HDL TestBench for 'sfir_fixed/symmetric_fir'.
### Begin simulation of the model 'gm_sfir_fixed'...
### Collecting data...
### Generating test bench: hdlsrc\sfir_fixed\symmetric_fir_tb.v
### Creating stimulus vectors...
### HDL TestBench generation complete.
The generated Verilog test bench code is saved in the hdlsrc\sfir_fixed folder.

Generate SystemVerilog DPI test bench for a subsystem.

Consider this option if generation or simulation of the default HDL test bench takes a long time. Generation of a DPI test bench can be faster than the default version because it does not run a Simulink® simulation to create the test bench data. Simulation of a DPI test bench with a large data set is faster than the default version because it does not store the input or expected data in a separate file. For requirements to use this feature, see the GenerateSVDPITestBench property.

Use makehdl to generate Verilog code for the subsystem symmetric_fir.

makehdl('sfir_fixed/symmetric_fir','TargetLanguage','Verilog')
### Generating HDL for 'sfir_fixed/symmetric_fir'.
### Starting HDL check.
### HDL check for 'sfir_fixed' complete with 0 errors, 0 warnings, 
    and 0 messages.
### Begin Verilog Code Generation for 'sfir_fixed'.
### Working on sfir_fixed/symmetric_fir as 
    hdlsrc\sfir_fixed\symmetric_fir.v
### HDL code generation complete.

After the code is generated, use makehdltb to generate a test bench for the same subsystem. Specify your HDL simulator so that the coder can generate scripts to build and run the generated SystemVerilog and C code. Disable generation of the default test bench.

makehdltb('sfir_fixed/symmetric_fir','TargetLanguage','Verilog',...
      'GenerateSVDPITestBench','ModelSim','GenerateHDLTestBench','off')
### Start checking model compatibility with SystemVerilog DPI testbench
### Finished checking model compatibility with SystemVerilog DPI testbench
### Preparing generated model for SystemVerilog DPI component generation
### Generating SystemVerilog DPI component
### Starting build procedure for model: gm_sfir_fixed_ref
### Starting SystemVerilog DPI Component Generation
### Generating DPI H Wrapper gm_sfir_fixed_ref_dpi.h
### Generating DPI C Wrapper gm_sfir_fixed_ref_dpi.c
### Generating SystemVerilog module gm_sfir_fixed_ref_dpi.sv using template C:\matlab\toolbox\hdlverifier\dpigenerator\rtw\hdlverifier_dpitb_template.vgt
### Generating makefiles for: gm_sfir_fixed_ref_dpi
### Invoking make to build the DPI Shared Library
### Successful completion of build procedure for model: gm_sfir_fixed_ref
### Working on symmetric_fir_dpi_tb as hdlsrc\sfir_fixed\symmetric_fir_dpi_tb.sv.
### Generating SystemVerilog DPI testbench simulation script for ModelSim/QuestaSim hdlsrc\sfir_fixed\symmetric_fir_dpi_tb.do

### HDL TestBench generation complete.
The generated SystemVerilog and C test bench files, and the build scripts, are saved in the hdlsrc\sfir_fixed folder.

Input Arguments

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DUT subsystem or model reference name, specified as a character vector, with full hierarchical path.

Example: 'modelname/subsysTarget'

Example: 'modelname/subsysA/subsysB/subsysTarget'

Name-Value Pair Arguments

Specify optional comma-separated pairs of Name,Value arguments. Name is the argument name and Value is the corresponding value. Name must appear inside quotes. You can specify several name and value pair arguments in any order as Name1,Value1,...,NameN,ValueN.

Example: 'TargetLanguage','Verilog'
Target Language and Folder Selection Options

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Specify the Subsystem in your model to generate the test bench for. For more information, see Generate HDL for.

Specify whether to generate VHDL or Verilog code. For more information, see Language.

Specify a path to write the generated files and HDL code into. For more information, see Folder.

Test Bench Generation Output Options

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The coder generates an HDL test bench by running a Simulink simulation to capture input vectors and expected output data for your DUT. For more information, see HDL test bench.

When you set this property, the coder generates a direct programming interface (DPI) component for your entire Simulink model, including your DUT and data sources. Your entire model must support C code generation with Simulink Coder™. The coder generates a SystemVerilog test bench that compares the output of the DPI component with the output of the HDL implementation of your DUT. The coder also builds shared libraries and generates a simulation script for the simulator you select.

Consider using this option if the default HDL test bench takes a long time to generate or simulate. Generation of a DPI test bench is sometimes faster than the default version because it does not run a full Simulink simulation to create the test bench data. Simulation of a DPI test bench with a large data set is faster than the default version because it does not store the input or expected data in a separate file. For an example, see Generate a SystemVerilog DPI Test Bench.

To use this feature, you must have HDL Verifier™ and Simulink Coder licenses. To run the SystemVerilog testbench with generated VHDL code, you must have a mixed-language simulation license for your HDL simulator.

Limitations

This test bench is not supported when you generate HDL code for the top-level Simulink model. Your DUT subsystem must meet the following conditions:

  • Input and output data types of the DUT cannot be larger than 64 bits.

  • Input and output ports of the DUT cannot use enumerated data types.

  • Input and output ports cannot be single-precision or double-precision data types.

  • The DUT cannot have multiple clocks. You must set the Clock inputs code generation option to Single.

  • Use trigger signal as clock must not be selected.

  • If the DUT uses vector ports, you must use Scalarize vector ports to flatten the interface.

See also SystemVerilog DPI test bench.

Generate an HDL Cosimulation block so you can simulate the DUT in Simulink with an HDL simulator.

For more information, see Cosimulation model.

Generate a model containing an HDL Cosimulation block for the specified HDL simulator.

For more information, see Cosimulation model.

Include code coverage switches in the generated build-and-run scripts. These switches turn on code coverage for the generated test bench. Specify your HDL simulator in the SimulationTool property. The coder generates build-and-run scripts for the simulator you specify.

For more information, see HDL code coverage.

This property applies to generated test benches. 'VCS' and 'Vivado' are supported only for SystemVerilog DPI test benches. When you select 'Custom', the tool uses the custom script settings. See the “Script Generation” properties.

For more information, see Simulation tool.

Clock and Reset Input Options

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Specify that the generated test bench drives the clock enable input based on ClockLowTime and ClockHighTime.

For more information, see Force clock.

Clock high time during a clock period, specified in nanoseconds.

For more information, see Clock high time (ns).

Clock low time during a clock period, specified in nanoseconds.

For more information, see Clock low time (ns).

Specify that the generated test bench drives the clock enable input.

For more information, see Force clock enable.

Number of clock cycles between deassertion of reset and assertion of clock enable, specified as a positive integer.

For more information, see Clock enable delay (in clock cycles)

Specify that the generated test bench drives the reset input.

For more information, see Force reset.

Length of time that reset is asserted, specified as the number of clock cycles.

For more information, see Reset length (in clock cycles).

Testbench Stimulus and Response Parameters

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Hold valid data between samples for signals clocked at slower rate.

For more information, see Hold input data between samples.

Hold time for inputs and forced reset, specified in nanoseconds.

For more information, see Hold time (ns).

Time after clock enable is asserted before starting output data checks, specified in number of samples.

For more information, see Ignore output data checking (number of samples).

Initialize test bench inputs to zero. For more information, see Initialize test bench inputs.

Testbench Configuration Parameters

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Postfix for test bench data file name, specified as a character vector.

For more information, see Test bench data file name postfix.

Postfix for test bench name, specified as a character vector.

For more information, see Test bench name postfix.

Postfix for test bench reference signal name, specified as a character vector.

For more information, see Test bench reference postfix.

Divide generated test bench into helper functions, data, and HDL test bench files.

For more information, see Multi-file test bench.

For more information, see Use file I/O to read/write test bench data.

Floating Point Tolerance Options

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Floating-point tolerance check based on relative error or ULP. For more information, see Floating point tolerance check based on.

Floating-point tolerance value depending on the FPToleranceStrategy specified. For more information, see Tolerance Value.

Port Names and Types

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Specify whether to generate single or multiple clock inputs in the HDL code. For more information, see Clock inputs.

Specify whether to use an active-high or active-low asserted level for the reset input signal. For more information, see Reset asserted level.

Specify the clock enable input port name as a character vector. For more information, see Clock enable input port.

Clock enable output port name, specified as a character vector.

For more information, see Clock Enable output port.

Specify the clock input port name as a character vector. For more information, see Clock input port.

Reset input port name, specified as a character vector.

For more information, see Reset input port.

File and Variable Names

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Specify the file name extension for generated Verilog files. For more information, see Verilog file extension.

Specify the file name extension for generated VHDL files. For more information, see VHDL file extension.

For more information, see VHDL architecture name.

For more information, see VHDL library name.

For more information, see Split entity file postfix.

For more information, see Split arch file postfix.

Specify the postfix for the package file name as a character vector. For more information, see Package postfix.

For more information, see Complex imaginary part postfix in Complex Signals Postfix Parameters.

For more information, see Complex real part postfix in Complex Signals Postfix Parameters.

Prefix for internal clock enable and control flow enable signals, specified as a character vector. For more information, see Clock Enable Settings and Parameters.

Coding Style

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For more information, see Split entity and architecture.

For more information, see Use Verilog `timescale directives.

For more information, see Emit time/date stamp in header in RTL Annotation Parameters.

For more information, see Inline VHDL configuration.

For more information, see Scalarize ports.

Script Generation

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For more information, see Compile initialization.

For more information, see Compile termination.

For more information, see Compile file postfix.

Verilog compilation command, specified as a character vector. The SimulatorFlags name-value pair specifies the first argument, and the module name specifies the second argument.

For more information, see Compile command for Verilog.

VHDL compilation command, specified as a character vector. The SimulatorFlags name-value pair specifies the first argument, and the entity name specifies the second argument.

For more information, see Compile command for VHDL.

The HDL simulation command, specified as a character vector.

For more information, see Simulation command.

Initialization for the HDL simulation script, specified as a character vector.

For more information, see Simulation initialization.

The termination name for the HDL simulation command, specified as a character vector.

For more information, see Simulation termination.

For more information, see Simulation file postfix.

Waveform viewing command, specified as a character vector. The implicit argument adds the signal paths for the DUT top-level input, output, and output reference signals.

For more information, see Simulation waveform viewing command.

See Also

Introduced in R2006b