Simple Dual Port RAM System

R2026b

Simple dual-port RAM that supports simultaneous read and write operations

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Simple Dual Port RAM System block

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Libraries:
HDL Coder / HDL RAMs

Description

The Simple Dual Port RAM System block models a simple dual-port RAM that supports simultaneous read and write operations. The block provides one output port for read data. To configure this block, open the block dialog box and set the Type of RAM block parameter to Simple dual port. The block accepts real or complex data.

Use this block to:

• Create parallel RAM banks by using vector data at the din, wr_addr, and we ports.

• Specify an initial value for the RAM by using the Initial output of RAM parameter.

• Model asynchronous read behavior in target hardware by selecting the Use asynchronous read feature in target hardware parameter.

• Model a cycle-accurate read operation by selecting the Model RAM with one cycle of delay parameter.

• Use the column-write method to write to specified bits in an addressed memory location.

Note

During a write operation, if a read operation occurs simultaneously at the same address, old data appears at the read output port.

Limitations

• When you build the FPGA bitstream, global reset logic does not reset RAM contents. To reset RAM contents, implement reset logic.

• RAM address inputs must be unsigned and must be between 2 and 31 bits long.

• The write enable input does not support signed data types with non-zero fraction lengths.

• The word length of the write data input must be a multiple of the word length of the write enable input.

• HDL code generation is not supported when Simple Dual Port RAM System blocks are in Resettable subsystems.

• You can generate HDL code for Simple Dual Port RAM System blocks that are in resettable subsystems.

• If the RAMArchitecture model configuration parameter is set to WithoutClockEnable, you cannot generate HDL code for Simple Dual Port RAM System blocks in enabled or triggered subsystems.

Ports

Input

din — Data to write

scalar | vector

Data to write, specified as a scalar or a vector. The block writes the value at port din to the memory location specified by wr_addr when the write enable signal at port we is true.

Bus Support:

Supports non-virtual buses and arrays of buses.

The block does not support:

• Nested bus at the data port.

• Non-zero values at the Initial output of RAM when you use a non-virtual bus input to the data port.

Data Types: single | double | half | int8 | int16 | uint8 | uint16 | Boolean | fixed point
Complex Number Support: Yes

wr_addr — Address to write

scalar | vector

Address to write, specified as an unsigned scalar or vector. The block uses this address to write to RAM when the signal at port we is true. The address must be unsigned and must be between 2 and 31 bits long.

Data Types: uint8 | uint16 | fixed point

we — Write enable

scalar | vector

Write enable control, specified as a scalar or a vector. When the signal at port we is true, the block writes the value at port din to the memory location specified by wr_addr. When the signal at port we is false, the block reads the value from the memory location specified by rd_addr port.

Note

To use the column-write method, specify the data type of we as an integer or fixed-point type.

Data Types: uint8 | uint16 | uint32 | uint64 | Boolean | fixed point

rd_addr — Address to read

scalar | vector

Address to read, specified as an unsigned scalar or vector. The block uses this address to read from the RAM. The address must be unsigned and must be between 2 and 31 bits long.

Dependencies

To enable this port, set the Type of RAM parameter to Simple dual port or Dual port.

Data Types: uint8 | uint16 | fixed point

Output

dout — Read output data

scalar | vector

Read output data, returned as a scalar or a vector. The block outputs the data stored at the memory location specified by the rd_addr input port. If a read and write occur simultaneously to the same address, the block outputs the old data.

Data Types: single | double | half | int8 | int16 | uint8 | uint16 | Boolean | fixed point
Complex Number Support: Yes

Parameters

Main

Type of RAM — RAM type

Simple dual port (default) | Dual port | Single port | True dual port | Simple tri port

Specify the RAM configuration. HDL Coder™ configures the input and output ports based on the RAM type you select.

• Single port — Create a single-port RAM with write data, address, and write enable data as inputs and read data as the output.

• Simple dual port — Create a simple dual-port RAM with write data, write address, write enable, and read address as inputs, and data from the read address as the output.

• Dual port — Create a dual-port RAM with write data, write address, write enable, and read address as inputs, and data from the read address and write address as the outputs.

• True dual port — Create a true dual-port RAM with write data a and b, write and read addresses for a and b, and write enable a and b as inputs and data from write addresses a and b as the outputs.

• Simple tri port — Create a simple tri port RAM with write data, write address, write enable, and read addresses a and b as inputs and data from read addresses a and b as the outputs.

Programmatic Use

Block Parameter: RAMType

Type: character vector, string

Values: Single port | Simple dual port | Dual port | True dual port | Simple tri port

Default: Simple dual port

Use asynchronous read feature in target hardware — Option to enable asynchronous read feature in target hardware

off (default) | on

Enable this option to allow the hardware to execute a read instruction immediately, without waiting one cycle.

Programmatic Use

Block Parameter: AsyncRead

Type: character vector, string

Values: 'on' | 'off'

Default: 'off'

Initial output of RAM — Initial simulation output of RAM

'0.0' (default) | Scalar | Vector

Specify the initial simulation output of the RAM by using one of these options:

• A scalar value.

• A vector with a one-to-one mapping between the initial value and the RAM words.

• An n-by-m matrix with a one-to-one mapping between the initial values and the RAM words in the RAM banks, where n represents the number of RAM banks and m represents the number of address locations in the RAM block, or vice-versa.

Programmatic Use

Block Parameter: RAMInitialValue

Type: integer, floating point

Values: 0.0 | Scalar | Vector

Default: 0.0

Data Types: single | double | int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64

Advanced

Model RAM with one cycle of delay — Model RAM with one cycle of delay

on (default) | off

Since R2024b

• When you select this parameter, the RAM delays the input data by one cycle before the output can read it. Use this option to ensure the block is cycle-accurate with the generated HDL code.

• When you clear this parameter, the RAM reads and outputs the input data immediately, but adds one cycle of latency during HDL code generation. Use this option to leverage clock-rate pipelining when you specify an oversampling value or work with multirate models.

Dependencies

To enable this parameter, clear the Use asynchronous read feature in target hardware parameter.

Programmatic Use

Block Parameter: ModelRAMDelay

Type: character vector, string

Values: 'on' | 'off'

Default: 'on'

Specify vector input access — Specify vector input access as serial or parallel

serial (default) | parallel

Since R2025a

• When you set this parameter to serial, the code generator infers parallel banks of RAM from vector inputs to RAM System block.

• When you set this parameter to parallel:

  • The code generator does not scale up RAM consumption with the size of the vector input when you generate HDL Code. Instead, it applies each operation of the input signals one at a time, starting with the first index. Enabling serial access allows you to leverage multicycle RAM access at a faster clock rate while modeling with a vector input at the data rate.

  • If the RAM System block exists in a clock-rate pipelining region, the serialization uses a clock-rate implementation instead of local multirate implementation.

Dependencies

To enable this parameter, clear the Model RAM with one cycle of delay parameter or enable the Use asynchronous read feature in target hardware parameter.

Programmatic Use

Block Parameter: VectorAccess

Type: character vector, string

Values: 'serial' | 'parallel'

Default: 'serial'

More About

Using the Column-Write Method to Selectively Write to Columns

You can use the column-write method to view the RAM as a collection of equally sized columns. During a write cycle, you can write into each of these columns separately. The data type and value of the write enable input, along with the data type of write data input, determine the size of each column and the columns in which the block writes in the addressed memory location.

In this context:

• DT is the data type of the write data input signal din.

• DW is the data width of the input data, which is equal to word length of the din value.

• DTWE is the data type of the write enable signal we. This signal determines which columns the block writes in the addressed memory location. The block writes the columns based on the position of the 1s in the binary representation of the value of we.

• NC is the number of columns which you can use to partition the RAM space to write the data, which is equal to word length of the we value.

• WC is the width of each column, which is equal to DW divided by NC.

The table summarizes the relationship among the data types of the write data input, the data types of write enable input, the number of columns, and the width of each column.

DT	DW	DTWE	NC	WC in Bits
uint16	16	ufix4	4	4
uint32	32	ufix4	4	8
uint64	64	ufix4	4	16
uint32	32	uint8	8	4
uint64	64	uint8	8	8
int32	32	uint16	16	2

For example, if DT is uint16 and WE is ufix4, then DW is equal to 16, NC is equal to 4, and WC is equal to 4 bits. If the input to din is 980, its binary representation is 0000001111010100. The column-wise representation of din is c4 = 0000, c3 = 0011, c2 = 1101, and c1 = 0100, where c1 is the first column.

The table summarizes the results of using the column-write method for different input combinations.

Value of we	Binary Representation of we	Columns Selected for Writing in RAM	Data at Memory Location		dout
			Before Performing Write Operation	After Performing Write Operation
3	0011	c2, c1	c4 = 0000 c3 = 0000 c2 = 0000 c1 = 0000	c4 = 0000 c3 = 0000 c2 = 1101 c1 = 0100	212
4	0100	c3	c4 = 0000 c3 = 0000 c2 = 0000 c1 = 0000	c4 = 0000 c3 = 0011 c2 = 0000 c1 = 0000	768
6	0110	c3, c2	c4 = 0000 c3 = 0000 c2 = 0000 c1 = 0000	c4 = 0000 c3 = 0011 c2 = 1101 c1 = 0000	976
9	1001	c4, c1	c4 = 0000 c3 = 0000 c2 = 0000 c1 = 0000	c4 = 0000 c3 = 0000 c2 = 0000 c1 = 0100	4
9	1001	c4, c1	c4 = 1111 c3 = 1111 c2 = 1111 c1 = 1111	c4 = 0000 c3 = 1111 c2 = 1111 c1 = 0100	4084

Limitations

• Inputs with signed data types and with non-zero fraction lengths are not supported by the write enable input port.

• The word length of the write data input must be a multiple of the word length of the write enable.

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation

Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

HDL Coder provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

The block has a MATLABSystem architecture which indicates that the block implementation uses the hdl.RAM System object™.

HDL Block Properties

General
ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays in the design. Distributed pipelining does not redistribute these registers. The default value is 0. For more details, see ConstrainedOutputPipeline.
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default value is 0. For more details, see InputPipeline.
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default value is 0. For more details, see OutputPipeline.
SynthesisAttributes	Specifies the synthesis attributes for the blocks and block output signals in the model. The generated HDL code contains these attributes. For more information, see SynthesisAttributes.

Optimizations

You can use HDL Coder optimizations to optimize speed, area, or I/O in the generated HDL code. For more information about enabling optimizations, see Enabling Optimizations in HDL Coder.

When you apply these optimizations to designs that include RAM blocks, HDL Coder may modify the surrounding logic that generates or consumes RAM addresses and data. However, the RAM block itself is preserved and mapped to the appropriate inferred RAM structure in the target FPGA or ASIC, ensuring consistent memory behavior.

Area Optimization

Optimization	Description
Resource Sharing	Resource sharing is an area optimization in which HDL Coder identifies multiple functionally equivalent resources and replaces them with a single resource. For more information, see Resource Sharing.
Streaming	Streaming is an area optimization in which HDL Coder transforms a vector data path to a scalar data path or to several smaller-sized vector data paths. For more information, see Streaming.

Speed Optimization

Optimization	Description
Distributed Pipelining	Distributed pipelining, or register retiming, is a speed optimization that moves existing delays in a design to reduce the critical path while preserving functional behavior. For more information, see Specify Distributed Pipelining Settings.
Clock-Rate Pipelining	Clock-rate pipelining is an optimization framework that allows other speed and area optimizations to introduce latency at the clock rate. For more information, see Clock-Rate Pipelining.
Adaptive Pipelining	Adaptive pipelining optimization creates patterns or combination of blocks with registers that can improve the achievable clock frequency and reduce the area usage on the FPGA boards by inserting pipeline registers to the blocks in your design. For more information, see Specify Adaptive Pipelining Settings.
Critical Path Estimation	To quickly identify the most likely critical path in your design, use critical path estimation. Critical Path Estimation estimation speeds up the iterative process of finding the critical path. To know blocks that are characterized in critical path estimation, see Characterized Blocks.

Version History

Introduced in R2017b

R2026a: RAMDirective HDL block property has been removed

The RAMDirective HDL block property has been removed. To map RAM blocks in your design to the RAM blocks on the target FPGA, use the SynthesisAttributes HDL block property instead.

R2026a: Specify synthesis attributes for blocks and block output signals

Use the SynthesisAttributes HDL block property to specify the synthesis attributes for the block and its output signals. HDL Coder includes these attributes in the generated HDL code.

R2024b: Use clock-rate pipelining

You can use Simple Dual Port RAM System block inside a data rate feedback loop and use clock-rate pipelining optimization. This model design is helpful for applications that require programmable or tunable lookup tables without having to regenerate bitstreams.

Use the new parameter Model RAM with one cycle of delay to model delay in your simulation. Model RAM with one cycle of delay is enabled by default and is disabled when Use asynchronous read feature in target hardware is enabled.

R2024b: Parameter name changes

These parameters are renamed:

Previous Name	Current Name
Specify the type of RAM	Type of RAM
Enable asynchronous reads	Use asynchronous read feature in target hardware
Specify the RAM initial value	Initial output of RAM

R2024b: Write to RAM in columns using column-write operations in RAM System blocks

In this block, you can use the column-write method to selectively modify specific parts of the memory without altering the remaining parts at a specified memory address.

R2024b: Initialize RAM banks with unique initial values for vector data inputs

In this block, you can initialize RAM banks with unique initial values.

R2024a: Array of Buses Input Support

The block now supports HDL code generation for input data specified as an array of buses.

R2024a: Half-Precision and Boolean Data Support

The block now supports HDL code generation with input data of type Half or Boolean.