Resource Sharing and Streaming

R2026b

Optimize area on target hardware

Reduce the resource usage of your design on a target FPGA or SoC device by applying area optimizations. You can reduce the area needed by your design by using resource sharing, and streaming optimizations.

Model Settings

expand all

Resource Sharing

Share Adders	Share adders with resource sharing optimization
Adder sharing minimum bitwidth	Minimum bit width required to share adders with resource sharing optimization
Share Multipliers	Share multipliers with resource sharing optimization
Multiplier sharing minimum bitwidth	Minimum bit width required to share multipliers with resource sharing optimization
Multiplier promotion threshold	Maximum bitwidth difference for promoting and sharing smaller multipliers
Multiplier partitioning threshold	Maximum input bit width for partitions
Multiply-Add blocks	Share Multiply-Add blocks with resource sharing optimization
Multiply-Add block sharing minimum bitwidth	Minimum bit width required to share Multiply-Add blocks with resource sharing optimization
Atomic subsystems	Share Atomic Subsystem blocks with resource sharing optimization
MATLAB Function blocks	Share MATLAB Function blocks with resource sharing optimization
Floating-Point IPs	Share floating-point IPs with resource sharing optimization

Topics

Resource Sharing
How to use resource sharing to save chip area.
Streaming
What is streaming and how to use the optimization to save resources.
Reduce Area by Sharing Multipliers in a Symmetric FIR Filter
This example shows how to use the resource sharing optimization in HDL Coder to reduce FPGA area by mapping multiple functionally equivalent multipliers to a single time-multiplexed multiplier.

Featured Examples

Streaming: Area Optimization

Use the subsystem level streaming optimization in HDL Coder™.

Open Script

Resource Sharing for Area Optimization

Use the subsystem level sharing optimization in HDL Coder™.

Open Script

Single-Rate Resource Sharing Architecture

How HDL Coder™ generates a single-rate architecture from a model to manage the execution of operations in the context of clock-rate pipelining and resource sharing. When you apply resource sharing to blocks in your design, HDL Coder decides the architecture to use based on the sample rate of the regions where sharing occurs. If resource sharing occurs in a region of the design that operates at the fastest base sample rate, then HDL Coder synthesizes a local multi-rate architecture, as described in Resource Sharing for Area Optimization. In this example, the shared resources are in a region that operates at a slower sample rate, so HDL Coder applies clock-rate pipelining and synthesizes a single-rate architecture.

Open Script

Improve Resource Sharing with Design Modifications

Improve opportunities for resource sharing to optimize your model design by making certain modifications to your design. Resource sharing is an HDL Coder optimization that improves area utilization in the design on the target FPGA device. The optimization identifies multiple functionally equivalent resources and replaces them with a single resource. For more information, see Resource Sharing.

Open Script

Improve Resource Sharing with Clone Detection and Replacement

Automatically identify and replace recurring patterns by using the docid:slcheck_ref#mw_9a8cbf44-2ac8-426a-9234-15ad575a4eb6 app. Consequently, it also improves opportunities for optimizing the model by using resource sharing. The Clone Detector app refactors models by identifying clones in a design and replacing clones with links to subsystem blocks in a library. This example uses a model that has already been modified for optimal resource sharing by using the Clone Detector app. To learn more about these modifications, see docid:hdlcoder_ug#example-hdlcoder_design_modification_sharing.

Open Live Script