Speed and Area Optimization

Improvements through resource sharing, streaming, pipelining, RAM mapping

For your target hardware, generate HDL code from a MATLAB^® function that meets timing and area requirements by using speed and area optimizations. Area optimizations reduce resource usage of your design. Speed optimizations improve the timing of your design on the target FPGA so that your design runs at higher frequencies by optimizing the critical path. To learn more about each type of optimization in HDL Coder™, see Speed and Area Optimizations in HDL Coder.

Functions

`coder.hdl.loopspec`	Unroll or stream loops in generated HDL and High-Level Synthesis (HLS) code
`coder.hdl.pipeline`	Insert pipeline registers at output of MATLAB expression
`coder.hdl.ramconfig`	Specify RAM mapping configuration for persistent array variables (Since R2023b)
`hdl.npufun`	Apply neighborhood processing and element-wise operations to incoming image or matrix for frame-to-sample conversion (Since R2022b)
`hdl.iteratorfun`	Apply iterative operation to an incoming image or matrix for frame-to-sample conversion (Since R2022b)

Topics

Optimization Basics

Speed and Area Optimizations in HDL Coder
Learn about various speed and area optimizations and how to optimize your design.
Specify the Clock Enable Rate
Configure clock enable to run at design base rate or input data rate.
Minimize Clock Enables
Generate code for registers without clock enables.
Constant Multiplier Optimization
What is Constant multiplier optimization and how to specify this optimization.

Area Optimization

Map Persistent Arrays and dsp.Delay Objects to RAM
Map persistent arrays and dsp.Delay objects to RAM on hardware to reduce the area used on your target device.
Map Matrices to ROM
To map a matrix constant to ROM:If your MATLAB code meets these requirements, HDL Coder inserts a no-reset register at the output of the matrix in the generated code.
Apply RAM Mapping to Optimize Area
Map elements to RAM to optimize area on your target hardware.
Map Matrices to Block RAMs to Reduce Area
This example shows how to use the RAM mapping optimization in HDL Coder™ to map persistent matrix variables to block RAMs in hardware.
Loop Streaming to Reduce Area
This example shows how to use the design-level loop streaming optimization in HDL Coder™ to optimize area.

Speed Optimization

Pipelining MATLAB Code
Pipelining helps achieve a higher maximum clock rate by inserting registers at strategic points in the hardware to break the critical path.
Pipeline MATLAB Expressions
Insert registers at output of MATLAB expression.
Optimize MATLAB Loops
Optimize loops for area or speed.
Distributed Pipelining
Distributed pipelining definition, benefits, and costs.
Clock-Rate Pipelining
Pipeline registers insertion at the faster clock rate instead of the slower data rate.

I/O Optimization

Use Neighborhood, Reduction, and Iterator Patterns with a Frame-Based Model or Function for HDL Code Generation
Generate HDL code from a frame-based design that models neighborhood, reduction, and iterator patterns.

Featured Examples

Optimize Clock Speed for MATLAB Code by Using Adaptive Pipelining

Use the adaptive pipelining optimization in HDL Coder to optimize clock speed for a MATLAB design.

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Distributed Pipelining for Clock Speed Optimization

Use the distributed pipelining and loop unrolling optimizations in HDL Coder™ to optimize clock speed.

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Resource Sharing of Multipliers to Reduce Area

Use the resource sharing optimization in HDL Coder™. This optimization identifies functionally equivalent multiplier operations in MATLAB® code and shares them in order to optimize design area. You have control over the number of multipliers to be shared in the design.

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Constant Multiplier Optimization to Reduce Area

Perform a design-level area optimization in HDL Coder™ by converting constant multipliers into shifts and adds using canonical signed digit (CSD) techniques. The CSD representation of multiplier constants for example, in gain coefficients or filter coefficients) significantly reduces the area of the hardware implementation.

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Optimize Feedback Loop Design and Maintain High Data Precision for HDL Code Generation

Optimize a feedback loop design and maintain high data precision for HDL code generation by using native floating point and clock-rate pipelining when generating HDL code from a MATLAB® design.

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