Main Content

Speed Optimization

Critical path estimation and reduction, pipeline register insertion, loop unrolling, automated iterative clock frequency optimization

Functions

hdlcoder.optimizeDesignAutomatic iterative HDL design optimization
hdlcoder.supportedDevicesShow supported target hardware and device details

Classes

hdlcoder.OptimizationConfighdlcoder.optimizeDesign configuration object

Blocks

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Deserializer1DConvert scalar stream or smaller vectors to vector signal
Multiply-AccumulatePerform a multiply-accumulate operation on the inputs
Multiply-AddMultiply-add combined operation
Serializer1DConvert vector signal to scalar or smaller vectors

Topics

Troubleshooting

Resolve Simulation Mismatch when Pipelining with a Feedback Loop Outside the DUT

Learn how to resolve simulation mismatch issues when using pipeline optimizations with feedback loops.