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Resolve Numerical Mismatch with Delay Balancing

This example shows how to use delay balancing to resolve a numerical mismatch between the generated model and original model after HDL code generation.

Problem

The issue is that simulating the validation model results in a numerical mismatch between the original model and the generated model after HDL code generation. To illustrate this issue:

1. Open the hdlcoder_resolve_delaybalancing model. The DUT is a simple multirate design.

modelname = 'hdlcoder_resolve_delaybalancing';
dutname = 'hdlcoder_resolve_delaybalancing/Subsystem';
load_system(modelname)
open_system(dutname)
set_param(modelname, 'SimulationCommand', 'update');

2. Generate HDL code and validation model for the DUT.

makehdl(dutname,'GenerateValidationModel', 'on', ...
                    'TargetDirectory','C:/Temp/hdlsrc')
### Generating HDL for 'hdlcoder_resolve_delaybalancing/Subsystem'.
### Using the config set for model <a href="matlab:configset.showParameterGroup('hdlcoder_resolve_delaybalancing', { 'HDL Code Generation' } )">hdlcoder_resolve_delaybalancing</a> for HDL code generation parameters.
### Running HDL checks on the model 'hdlcoder_resolve_delaybalancing'.
### Begin compilation of the model 'hdlcoder_resolve_delaybalancing'...
### Applying HDL optimizations on the model 'hdlcoder_resolve_delaybalancing'...
### Begin model generation.
### Model generation complete.
### Generating new validation model: <a href="matlab:open_system('gm_hdlcoder_resolve_delaybalancing_vnl')">gm_hdlcoder_resolve_delaybalancing_vnl</a>.
### Validation model generation complete.
### Begin VHDL Code Generation for 'hdlcoder_resolve_delaybalancing'.
### MESSAGE: The design requires 3 times faster clock with respect to the base rate = 0.1.
### Working on hdlcoder_resolve_delaybalancing/Subsystem/Sqrt/Sqrt_iv as C:/Temp/hdlsrc/hdlcoder_resolve_delaybalancing/Sqrt_iv.vhd.
### Working on hdlcoder_resolve_delaybalancing/Subsystem/Sqrt/Sqrt_core as C:/Temp/hdlsrc/hdlcoder_resolve_delaybalancing/Sqrt_core.vhd.
### Working on hdlcoder_resolve_delaybalancing/Subsystem/Sqrt as C:/Temp/hdlsrc/hdlcoder_resolve_delaybalancing/Sqrt.vhd.
### Working on Subsystem_tc as C:/Temp/hdlsrc/hdlcoder_resolve_delaybalancing/Subsystem_tc.vhd.
### Working on hdlcoder_resolve_delaybalancing/Subsystem as C:/Temp/hdlsrc/hdlcoder_resolve_delaybalancing/Subsystem.vhd.
### Generating package file C:/Temp/hdlsrc/hdlcoder_resolve_delaybalancing/Subsystem_pkg.vhd.
### Code Generation for 'hdlcoder_resolve_delaybalancing' completed.
### Creating HDL Code Generation Check Report file:///tmp/Bdoc21a_1606923_56719/tp785760dd/ex37089823/C:/Temp/hdlsrc/hdlcoder_resolve_delaybalancing/Subsystem_report.html
### HDL check for 'hdlcoder_resolve_delaybalancing' complete with 0 errors, 2 warnings, and 4 messages.
### HDL code generation complete.

3. View the validation model. The validation model compares the generated model with the original model. The generated model displays the effect of optimizations and block-specific architectures that you specify. Use the validation model to verify that the DUT in the generated model is bit-true to the numerical results produced by the original DUT.

valmodelname = 'gm_hdlcoder_resolve_delaybalancing_vnl';
valmodelsubsys = 'gm_hdlcoder_resolve_delaybalancing_vnl/Subsystem';
load_system(valmodelname)
open_system(valmodelsubsys)
set_param(valmodelname, 'SimulationCommand', 'update');

4. Simulate the validation model. HDL Coder™ generates warnings that indicate an assertion detected at various time stamps. If you navigate through the validation model by double-clicking the Compare Subsystem and then the Assert_Out1 Subsystem, you see a compare: Out1 Scope block. This Scope block compares the output of the original model DUT with the generated model DUT and displays numerical differences as an error signal. When you double-click the Scope block, you see a nonzero error, which indicates a numerical mismatch.

Cause

To diagnose this issue:

1. Observe the parameters saved on the original model. You see that BalanceDelays is set to off on the model.

hdlsaveparams(modelname)
%% Set Model 'hdlcoder_resolve_delaybalancing' HDL parameters
hdlset_param('hdlcoder_resolve_delaybalancing', 'BalanceDelays', 'off');
hdlset_param('hdlcoder_resolve_delaybalancing', 'GenerateHDLTestBench', 'off');
hdlset_param('hdlcoder_resolve_delaybalancing', 'GenerateValidationModel', 'on');
hdlset_param('hdlcoder_resolve_delaybalancing', 'HDLSubsystem', 'hdlcoder_resolve_delaybalancing/Subsystem');

% Set Gain HDL parameters
hdlset_param('hdlcoder_resolve_delaybalancing/Subsystem/Gain3', 'OutputPipeline', 2);

hdlset_param('hdlcoder_resolve_delaybalancing/Subsystem/Sqrt', 'Architecture', 'RecipSqrtNewton');

2. Inspect the validation model. Inside the DUT Subsystem, you see that the code generator implemented the reciprocal square root operation as a Subsystem. If you double-click the Sqrt Subsystem, you see that the implementation has a latency. This latency arises due to the Newton-Raphson implementation of reciprocal square root.

open_system('gm_hdlcoder_resolve_delaybalancing_vnl/Subsystem/Sqrt')

The simulation mismatch occurred because the Newton-Raphson choice for implementing the Reciprocal Sqrt block results in a latency difference between the original model and the generated model. In addition, the downsampling introduced by the Rate Transition block drops samples. As delay balancing is disabled on the model, the code generator did not add matching delays to account for this latency.

Solution

To fix this issue, enable delay balancing on the model. In the original model, set BalanceDelays to on. When you enable delay balancing, the code generator detects introduction of delays along one path and adds matching delays on other, parallel signal paths.

1. Enable BalanceDelays on the model and generate HDL code and validation model.

load_system(modelname)
makehdl(dutname,'BalanceDelays','on', ...
                'GenerateValidationModel', 'on', ...
                    'TargetDirectory','C:/Temp/hdlsrc')
### Generating HDL for 'hdlcoder_resolve_delaybalancing/Subsystem'.
### Using the config set for model <a href="matlab:configset.showParameterGroup('hdlcoder_resolve_delaybalancing', { 'HDL Code Generation' } )">hdlcoder_resolve_delaybalancing</a> for HDL code generation parameters.
### Running HDL checks on the model 'hdlcoder_resolve_delaybalancing'.
### Begin compilation of the model 'hdlcoder_resolve_delaybalancing'...
### Applying HDL optimizations on the model 'hdlcoder_resolve_delaybalancing'...
### The code generation and optimization options you have chosen have introduced additional pipeline delays.
### The delay balancing feature has automatically inserted matching delays for compensation.
### The DUT requires an initial pipeline setup latency. Each output port experiences these additional delays.
### Output port 1: 2 cycles.
### Begin model generation.
### Model generation complete.
### Generating new validation model: <a href="matlab:open_system('gm_hdlcoder_resolve_delaybalancing_vnl')">gm_hdlcoder_resolve_delaybalancing_vnl</a>.
### Validation model generation complete.
### Begin VHDL Code Generation for 'hdlcoder_resolve_delaybalancing'.
### MESSAGE: The design requires 3 times faster clock with respect to the base rate = 0.1.
### Working on hdlcoder_resolve_delaybalancing/Subsystem/Sqrt/Sqrt_iv as C:/Temp/hdlsrc/hdlcoder_resolve_delaybalancing/Sqrt_iv.vhd.
### Working on hdlcoder_resolve_delaybalancing/Subsystem/Sqrt/Sqrt_core as C:/Temp/hdlsrc/hdlcoder_resolve_delaybalancing/Sqrt_core.vhd.
### Working on hdlcoder_resolve_delaybalancing/Subsystem/Sqrt as C:/Temp/hdlsrc/hdlcoder_resolve_delaybalancing/Sqrt.vhd.
### Working on Subsystem_tc as C:/Temp/hdlsrc/hdlcoder_resolve_delaybalancing/Subsystem_tc.vhd.
### Working on hdlcoder_resolve_delaybalancing/Subsystem as C:/Temp/hdlsrc/hdlcoder_resolve_delaybalancing/Subsystem.vhd.
### Generating package file C:/Temp/hdlsrc/hdlcoder_resolve_delaybalancing/Subsystem_pkg.vhd.
### Code Generation for 'hdlcoder_resolve_delaybalancing' completed.
### Creating HDL Code Generation Check Report file:///tmp/Bdoc21a_1606923_56719/tp785760dd/ex37089823/C:/Temp/hdlsrc/hdlcoder_resolve_delaybalancing/Subsystem_report.html
### HDL check for 'hdlcoder_resolve_delaybalancing' complete with 0 errors, 0 warnings, and 4 messages.
### HDL code generation complete.

2. Open the validation model. You see that the code generator introduced matching delays to balance the latency introduced by the Sqrt block and to offset the effect of downsampling. The additional delays account for the latency difference.

load_system(valmodelname)
open_system(valmodelsubsys)
set_param(valmodelname, 'SimulationCommand', 'update');

3. Simulate the validation model and open the compare: Out1 Scope block. You see that the numerical mismatch has been resolved.

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