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Generate Code with Annotations or Comments

You can use the HDL Coder™ software to add text annotations to generated code in the form of model annotations, text comments, or requirements comments.

Simulink Annotations

When you enter text directly on the block diagram as Simulink® annotations, HDL Coder renders the text from these Simulink annotations as plain text comments in generated code. The comments are generated at the same level in the model hierarchy as the subsystem that contains the annotations.

For Constant blocks, to reflect the annotations as comments in the HDL code, clear the Minimize Intermediate Signals check box and set Traceability style to Comment Based.

See Annotate Models for more information about annotations.

Signal Descriptions

When you provide a description for the signals in your Simulink model, the generated HDL code displays these descriptions as comments above the signal declaration statements. To specify a description for the signal, right-click the signal and select Properties to open the Signal Properties dialog box. Then, select the Documentation tab, and in the Description section, enter a description for the signal. For the signal description, use ASCII characters. Non-ASCII characters in the generated code may potentially interfere with downstream synthesis and lint tools. In some cases, due to optimizations that act on the signals, the generated code may not translate all signal descriptions to HDL comments or may create replicas of HDL comments for certain signal descriptions.

Text Comments

If enter text comments in your model by using a DocBlock block and entering text comments, HDL Coder renders the text from the DocBlock block in the generated code as plain text comments. The comments are generated at the same level in the model hierarchy as the subsystem that contains the DocBlock block.

Set the Document type parameter of the DocBlock to Text. HDL Coder does not support the HTML or RTF options.

For more information about the DocBlock block, see DocBlock.

Requirement Comments and Hyperlinks

By using the Requirements Toolbox™, you can assign requirements to blocks and generate them as comments in the generated code. For example:

  1. Open the model hdlcoder_simple_up_counter using this command:

    openExample("hdlcoder_simple_up_counter");

  2. Create a new requirement set named Delay_requirements.slreqx by using the Requirements Editor (Requirements Toolbox) with these details:

    • Custom ID: 1

    • Summary: Requirement 1

    • Description: Sample text 1

    Similarly, create another requirement with these details:

    • Custom ID: 2

    • Summary: Requirement 2

    • Description: Sample text 2

    For more information, see Author Requirements in MATLAB or Simulink (Requirements Toolbox).

  3. Open the HDL_DUT subsystem.

  4. Right-click the Delay block named Delay. From the context menu, select Requirements > Open Outgoing Links dialog.

  5. Link the requirements for block. Click the New button. Enter details about the requirement by using the Description, Document type, Document, and Location (Type/Identifier) properties.

    Outgoing Links diaglog box with sample details filled out such as Description, Document type, Document, and Location.

  6. Click Apply and OK.

  7. To include requirements as hyperlinked comments in the generated code, in the Configuration Parameters dialog box, select these model configuration parameters:

    • Generate traceability report

    • Include requirements in block comments

    Alternatively, if you generate code from the command line, set the Traceability and RequirementComments properties.

    makehdl("HDL_DUT","Traceability","on","RequirementComments","on");
    

    The generated code shows the requirements as comments for the Delay block in the hdlcoder_simple_up_counter model. The comments include links to the requirements associated with the block and in the original model.

      -- <S1>/Delay
      -- Block requirements for <S1>/Delay
      --  1. Requirements 1
      --  2. Requirements 2
      Delay_process : PROCESS (clk, reset)
      BEGIN
        IF reset = '1' THEN
          Delay_out1 <= to_unsigned(16#00#, 8);
        ELSIF clk'EVENT AND clk = '1' THEN
          IF enb = '1' THEN
            Delay_out1 <= Switch1_out1;
          END IF;
        END IF;
      END PROCESS Delay_process;

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