You can follow these guidelines to learn how to use blocks that can perform rate conversions in your model and blocks from the Sources library such as Constant blocks in your design. Each guideline has a severity level that indicates the level of compliance requirements. To learn more, see HDL Modeling Guidelines Severity Levels.
There are various ways in which you can model rate transitions. How you model rate transitions determine the timing and resource requirements of your design. This guideline shows various approaches for modeling rate transitions.
Increasing the Sample Rate. This table illustrates the blocks that you can use to increase the sample rate of your design. When you use these blocks, leave the block parameters to the default settings.
Rate Conversion Approach
|Block||Generates Bypass Register?||Generates Zero Padding?||Notes|
|Repeat||No||No||To use this block, you must have DSP System Toolbox™ installed.|
|Upsample||Yes||Yes||To use this block, you must have DSP System Toolbox installed. When you use this block, consider the impact of the bypass register and the logic that inserts zero padding on hardware resource usage.|
For the Rate Transition block, to upsample the input signal without incurring a unit delay, in the Block Parameters dialog box of the Rate Transition block:
Clear the Ensure data integrity during data transfer check box.
Clearing this check box makes the Ensure deterministic data transfer (maximum delay) check box to disappear.
Configure the output port sample time of the block to be an
integer multiple of the input port sample time. Specify a
fractional value of
1/n for Sample
time multiple where
n is an
integer. You can choose any value
for the block parameter Output port sample time
options as long as Sample time
multiple uses a value
When the input and output clocks are not synchronous to each other, to avoid insertion of a bypass register in the HDL code generated for the Repeat and Rate Transition blocks, insert one unit delay following the Repeat and Rate Transition blocks in your model.
Decreasing the Sample Rate. To reduce the sample rate, you can use a DownSample or a Rate Transition block. To use the Downsample block, you must have DSP System Toolbox installed. When you use these blocks, leave the block parameters to the default settings.
When downsampling the input signal, use the Rate Transition block because you can leave the block parameters to the default settings for HDL code generation. The Ensure data integrity during data transfer and Ensure deterministic data transfer (maximum delay) check boxes must be left selected. This mode generates an additional bypass register in the HDL code.
You use the Initial Condition parameter of the block when reducing the sample rate. This parameter setting is not used when the code generator increases the sample rate.
By default, the sample time of a Constant block is
inf. When you connect a Constant block
with sample time of
inf to other blocks in your design, it
hinders speed and area optimizations. Optimizations such as retiming, sharing,
and streaming use the clock rate information to improve the speed and area of
When you use the Constant block, set the sample time of the
-1. To identify Constant blocks that
have infinite sample time in your design, in the Simulink® model window, In the Debug tab, on the Information Overlays > Sample Time section, select Colors. The Sample Time
Legend then displays the Constant blocks that have
Inf sample time.
You can identify and change the sample time of all
Constant blocks to
-1 by using either of these approaches:
Run a script that can programmatically change the sample time of
the blocks to
-1. For an example script, see
Identify and Programmatically Change and Display HDL Block Parameters.
Run the check Check for infinite and continuous sample time sources in the HDL Code Advisor. If running the check fails, it displays
sources such as Constant blocks that have infinite
sample time. Select Modify Settings to update
the sample time to
-1 or to inherit via