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Multi-Tile Synchronization

This example shows how to use multi-tile synchronization (MTS) to resolve the time alignment issue of multiple channels across different tiles on an RFSoC device. The RFSoC has built-in features that enforce the time alignment for samples of multiple channels across different tiles. Channels in a tile alone are aligned in time but a guarantee of alignment with another channel from a different tile does not exist. You can enable multi-tile synchronization (MTS) to correct for this issue by first measuring latency across different tiles and then applying sample delays to ensure samples align correctly.

MTS for Xilinx® Zynq® UltraScale+™ RFSoC ZCU111 and Xilinx Zynq UltraScale+ RFSoC ZCU216 evaluation kits requires that you chose specific sample rates that are governed by SYSREF signals from an external clock. According to Xilinx datasheet PG269, the SYSREF frequency must meet these requirements.

  • If synchronizing RF-ADC and RF-DAC tiles with the different sample frequencies, the frequency must be an integer submultiple of: GCD(DAC_Sample_Rate/16, ADC_Sample_Rate/16).

  • SYSREF must also be an integer submultiple of all PL clocks that sample it. This is to ensure the periodic SYSREF is always sampled synchronously.

  • Less than 10 MHz.

In the context of the ZCU111 and ZCU216 boards, the reference clock must be an integer multiple of the SYSREF frequency. For the ZCU111 board, the default SYSREF frequency produced by the LMK is 7.68 MHz. To meet the requirements, choose a sampling rate from the available provided frequencies from the LMK that is a multiple of 7.68 MHz.

In many designs, this reference clock is chosen in such a way to satisfy this requirement. For example, 245.76 MHz is a common choice when you use a ZCU216 board. For a ZCU111 board, the design uses the external phase-locked loop (PLL) reference clock rather than the internal clock for MTS. The configuration files and System object™ scripts that are generated during the HDL Workflow Advisor step complete this process.


  • Vivado® Design Suite with a supported version listed in Supported EDA Tools and Hardware

  • Xilinx Zynq UltraScale+ ZCU111 evaluation kit or Xilinx Zynq UltraScale+ ZCU216 evaluation kit

  • HDL Coder

  • HDL Coder Support Package for Xilinx FPGA and SoC Devices

Open Example

Open the example project and copy the example files to a temporary directory.

1. Navigate to the RFSoC root example directory of HDL Coder Support Package for Xilinx FPGA and SoC Devices by entering these commands at the MATLAB® command prompt.

example_root = (hdlcoder_rfsoc_examples_root)
cd (example_root)

2. Copy all of the example files in the MTS folder to a temporary directory.

MTS Cable Setup

This example provides two MTS examples, one for a ZCU111 board and one for a ZCU216 board. These examples show that analog-to-digital converter (ADC) channel samples from different tiles are aligned after you apply MTS. By comparing one channel with the other, visual inspection can be performed.

When using Multi-Tile Synchronization, use ADC and DAC channels that are connected to the differential SMA ports on the XM500. The single-ended baluns introduce amplitude and phase offset between channels even when MTS is enabled.

For comparing channels, the ZCU111 example cable setup for the XM500 balun card is configured so that it compares two channels from differing tiles. These two figures show the cable setup.

In these figures:

  • DAC 00 connects to ADC 04.

  • DAC 01 connects to ADC 07.

In terms of tile connections, the setup that these figures show represents 0-based indexing.

  • DAC Tile 0 Channel 0 connects to ADC Tile 2 Channel 0.

  • DAC Tile 0 Channel 1 connects to ADC Tile 3 Channel 2.

Differential cables that have DC blockers are used to make use of the differential ports. The cables use a data path that does not have an analog RF cage filter, which can impose phase delays across different channels. Because the purpose of this test is to measure sample alignment, avoiding things that can potentially alter results, such as a mismatch in cable types or filters, is a best practice.

For the ZCU216 board, a similar setup is used with differential SMA connections by using the XM655 balun card. This figure shows the XM655 board with a differential cable.

ADC Setup

DAC Setup

In the DAC setup figure:

  • DAC P/N 0_228 connects to ADC P/N 02_224.

  • DAC P/N 0_229 connects to ADC P/N 00_225.

The next two figures show a schematic that indicates which differential connectors this example uses.



In terms of tile connections, the setup that these figures show represents 0-based indexing.

  • DAC Tile 0 Channel 0 connects to ADC Tile 0 Channel 2.

  • DAC Tile 1 Channel 0 connects to ADC Tile 1 Channel 2.

For more information on cable setups, see the Xilinx documentation.

HDL Model and Bitstream Synthesis

Two HDL models (rfsoc_zcu216_MTS_iq_HDL.slx and rfsoc_zcu111_MTS_iq_HDL.slx located in the example root) are provided for the ZCU216 and ZCU111 boards. The models take in two channels for data capture selected by an AXI4 register for routing. Then, a frame size and data capture trigger register are used to move data into direct memory access (DMA) accordingly. An additional mux is added to pick between inphase (I) or quadrature (Q) when comparing the channels. Because the design runs at four samples per clock for in-phase and quadrature (IQ), a limited amount of data width is available for moving data across.

To synthesize HDL, right-click the subsystem. Select HDL Code, then click HDL Workflow Advisor. In step 1.1 of the HDL Workflow Advisor, select Target platform as Xilinx Zynq Ultrascale+ RFSoC ZCU111 Evaluation Kit or Xilinx Zynq Ultrascale+ RFSoC ZCU216 Evaluation Kit.

In step 1.2, set these reference design parameters to the indicated values.

  • AXI4-Stream DMA data width to 128

  • ADC sampling rate (MHz) to 1966.08

  • ADC decimation mode (xN) to 4

  • ADC samples per clock cycle to 4

  • ADC mixer type to Fine

  • DAC sampling rate (MHz) to 1966.08

  • DAC interpolation mode (xN) to 4

  • DAC samples per clock cycle to 4

  • DAC mixer type to Fine

  • ADC/DAC NCO mixer LO (GHz) to 0.5

  • Enable multi-tile sync to true

If you are using a ZCU216 board, additionally set the DAC DUC mode parameter to Full DUC Nyquist (0-Fs/2).

Afterward, build the bitstream and then program the board.

Run-Time Testing of MTS Channel Alignment

After you program the board, it reboots and initializes with MTS applied when Linux® loads. To configure the RFSoC with various properties and settings, use a configuration CFG file.

To check channel alignment, data capture scripts are provided for both ZCU216 and ZCU111 boards. If the SMA attachment cards match the setup described in the previous sections of this example, run the script. The results show near-perfect alignment of the channels.

Run whichever script matches the board that you are testing against.


A single plot shows the result of the data capture of two channels.

When you use MTS, avoid changing the digital local oscillator (LO) of the RFSoC during MTS. The LO for each channel might not be aligned in time, which can impact alignment. The RFSoC provides ways of dealing with this issue by synchronizing the reset condition on all channels based on tile events. By setting tile events to listen to a SYSREF signal, alignment can be achieved when you use the mixer during an MTS routine. The SYSREF capture must be disabled first, then the change to the LO is applied, and then an MTS calibration is done again. To see an example of this process, run the script ZCU216_ChangeLO.m or ZCU111_ChangeLO.m.