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HDL Coder

Generate Verilog, SystemVerilog, and VHDL code for FPGA and ASIC designs

HDL Coder™ enables high-level design for FPGAs, SoCs, and ASICs by generating portable, synthesizable Verilog®, SystemVerilog, and VHDL® code from MATLAB® functions, Simulink® models, and Stateflow® charts. You can use the generated HDL code for FPGA programming, ASIC prototyping, and production design.

HDL Coder includes a workflow advisor that automates prototyping generated code on Xilinx®, Intel®, and Microchip boards and generates IP cores for ASIC and FPGA workflows. You can optimize for speed and area, highlight critical paths, and generate resource utilization estimates before synthesis. HDL Coder provides traceability between Simulink models and the generated Verilog, SystemVerilog, and VHDL code, enabling code verification for high-integrity applications adhering to DO-254 and other standards.

Get Started

Learn the basics of HDL Coder

HDL Code Generation from MATLAB

Generate HDL Code from MATLAB algorithms

HDL Code Generation from Simulink

Generate HDL code from Simulink models

High-Level Synthesis Code Generation from MATLAB

Generate High-Level Synthesis Code from MATLAB algorithms

Targeting FPGA & SoC Hardware

Deploy generated HDL code on a target hardware platform

HDL Coder Supported Hardware

Support for third-party hardware, such as Intel, Microchip, and Xilinx FPGA boards

Tool Qualification and Certification

Qualify HDL Coder for IEC certification