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Implement Reciprocal Block with Control Signals

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This example shows how to implement the control-signal based Reciprocal block and use it to generate HDL code.

Open and Run Simulink Model

Specify the input data values as a linear sweep. You can change these values according to your requirements

reciprocal_input = fi(1/2^10:1/2^18:1,0,18,18)';

Specify the word length for fixed-point datatypes and the latency for the model. For more information on the latency calculation, see Reciprocal.

WL_recip = 18;  recip_latency = 41;

Open the hdlcoder_reciprocal_shiftadd_control model and specify a stop time sufficient to process all the input combinations.

stoptime_recip = length(reciprocal_input)-1+recip_latency;
open_system('hdlcoder_reciprocal_shiftadd_control')
sim('hdlcoder_reciprocal_shiftadd_control')

This figure shows the output waveform when you simulate the model. The dataOut output is valid when validOut is 1.

Validate Simulink Output By Using Reference Output

To validate the output of the Simulink model, compare this output with a reference values. Compute the reference output by using the reciprocal operation.

ref_reciprocal = 1./double(reciprocal_input);

Use logical indexing to extract valid output.

implementation_reciprocal = simulink_reciprocal(valid_output);

Plot the comparison results by using the comparison_plot_reciprocal function. The maximum error value is significantly smaller than the output of the model.

comparison_plot_reciprocal(ref_reciprocal,implementation_reciprocal,9,'reciprocal linear input');

Maximum Error reciprocal linear input 1.525867e-05 
Maximum PctError reciprocal linear input 1.522159e-03

Generate HDL Code for Reciprocal Implementation

Check HDL settings of the model by using the hdlsaveparams function.

hdlsaveparams('hdlcoder_reciprocal_shiftadd_control')

%% Set Model 'hdlcoder_reciprocal_shiftadd_control' HDL parameters
hdlset_param('hdlcoder_reciprocal_shiftadd_control', 'Backannotation', 'on');
hdlset_param('hdlcoder_reciprocal_shiftadd_control', 'HDLSubsystem', 'hdlcoder_reciprocal_shiftadd_control/Reciprocal');
hdlset_param('hdlcoder_reciprocal_shiftadd_control', 'ResetType', 'Synchronous');
hdlset_param('hdlcoder_reciprocal_shiftadd_control', 'ResourceReport', 'on');
hdlset_param('hdlcoder_reciprocal_shiftadd_control', 'SynthesisTool', 'Xilinx Vivado');
hdlset_param('hdlcoder_reciprocal_shiftadd_control', 'SynthesisToolChipFamily', 'Virtex7');
hdlset_param('hdlcoder_reciprocal_shiftadd_control', 'SynthesisToolDeviceName', 'xc7v2000t');
hdlset_param('hdlcoder_reciprocal_shiftadd_control', 'SynthesisToolPackageName', 'fhg1761');
hdlset_param('hdlcoder_reciprocal_shiftadd_control', 'SynthesisToolSpeedValue', '-2');
hdlset_param('hdlcoder_reciprocal_shiftadd_control', 'TargetDirectory', 'hdl_prj\hdlsrc');
hdlset_param('hdlcoder_reciprocal_shiftadd_control', 'TargetFrequency', 500);
hdlset_param('hdlcoder_reciprocal_shiftadd_control', 'Traceability', 'on');

% Set SubSystem HDL parameters
hdlset_param('hdlcoder_reciprocal_shiftadd_control/Reciprocal', 'FlattenHierarchy', 'on');

hdlset_param('hdlcoder_reciprocal_shiftadd_control/Reciprocal/LumpLatency', 'Architecture', 'MATLAB Datapath');
% Set SubSystem HDL parameters
hdlset_param('hdlcoder_reciprocal_shiftadd_control/Reciprocal/LumpLatency', 'FlattenHierarchy', 'on');

hdlset_param('hdlcoder_reciprocal_shiftadd_control/Reciprocal/Reciprocal', 'Architecture', 'ShiftAdd');

hdlset_param('hdlcoder_reciprocal_shiftadd_control/Reciprocal/ValidLine', 'Architecture', 'MATLAB Datapath');
% Set SubSystem HDL parameters
hdlset_param('hdlcoder_reciprocal_shiftadd_control/Reciprocal/ValidLine', 'FlattenHierarchy', 'on');

To generate HDL code for the Reciprocal block in the model, use the makehdl function.

makehdl('hdlcoder_reciprocal_shiftadd_control/Reciprocal')
close_system('hdlcoder_reciprocal_shiftadd_control')
close all;

### Generating HDL for 'hdlcoder_reciprocal_shiftadd_control/Reciprocal'.
### Using the config set for model <a href="matlab:configset.showParameterGroup('hdlcoder_reciprocal_shiftadd_control', { 'HDL Code Generation' } )">hdlcoder_reciprocal_shiftadd_control</a> for HDL code generation parameters.
### Running HDL checks on the model 'hdlcoder_reciprocal_shiftadd_control'.
### Begin compilation of the model 'hdlcoder_reciprocal_shiftadd_control'...
### Begin compilation of the model 'hdlcoder_reciprocal_shiftadd_control'...
### Working on the model 'hdlcoder_reciprocal_shiftadd_control'...
### <a href="matlab:configset.internal.open('hdlcoder_reciprocal_shiftadd_control','AdaptivePipelining')">'AdaptivePipelining'</a> is set to 'Off' for the model. 'AdaptivePipelining' can improve the achievable clock frequency and reduce the area usage on FPGA boards. To enable adaptive pipelining, please set the option to 'On'. When adaptive pipelining is enabled, it inserts pipeline registers to create patterns that efficiently map blocks to DSP units on the target FPGA device.
### <a href="matlab:configset.internal.open('hdlcoder_reciprocal_shiftadd_control','LUTMapToRAM')">'LUTMapToRAM'</a> is set to 'On' for the model. This option is used to map lookup tables to a block RAM in hardware.  To disable pipeline insertion for mapping lookup tables to RAM, please set the option to 'Off'.
### Working on... <a href="matlab:configset.internal.open('hdlcoder_reciprocal_shiftadd_control', 'GenerateModel')">GenerateModel</a>
### Begin model generation 'gm_hdlcoder_reciprocal_shiftadd_control' ....
### Rendering DUT with optimization related changes (IO, Area, Pipelining)...
### Model generation complete.
### Begin VHDL Code Generation for 'hdlcoder_reciprocal_shiftadd_control'.
### Working on... <a href="matlab:configset.internal.open('hdlcoder_reciprocal_shiftadd_control', 'Traceability')">Traceability</a>
### Working on hdlcoder_reciprocal_shiftadd_control/Reciprocal/Reciprocal as hdl_prj/hdlsrc/hdlcoder_reciprocal_shiftadd_control/Reciprocal_block.vhd.
### Working on hdlcoder_reciprocal_shiftadd_control/Reciprocal as hdl_prj/hdlsrc/hdlcoder_reciprocal_shiftadd_control/Reciprocal.vhd.
### Code Generation for 'hdlcoder_reciprocal_shiftadd_control' completed.
### Generating HTML files for code generation report at <a href="matlab:web('/tmp/Bdoc23b_2361005_1061343/tpe92f0394/hdlcoder-ex85473417/hdl_prj/hdlsrc/hdlcoder_reciprocal_shiftadd_control/html/hdlcoder_reciprocal_shiftadd_control_codegen_rpt.html')">hdlcoder_reciprocal_shiftadd_control_codegen_rpt.html</a>
### Creating HDL Code Generation Check Report file:///tmp/Bdoc23b_2361005_1061343/tpe92f0394/hdlcoder-ex85473417/hdl_prj/hdlsrc/hdlcoder_reciprocal_shiftadd_control/Reciprocal_report.html
### HDL check for 'hdlcoder_reciprocal_shiftadd_control' complete with 0 errors, 1 warnings, and 2 messages.
### HDL code generation complete.

Reciprocal Block Synthesis Performance

This figure shows the Reciprocal block synthesis performance on the Xilinx® Virtex® 7 and Intel® Stratix® V devices.