A mapping from Stateflow® semantics to an HDL implementation has the following requirements:
Requirement 1: Hardware designs require separability of output and state update functions.
Requirement 2: HDL is a concurrent language. To achieve the goal of bit-true simulation, execution must be in order.
To meet Requirement 1, an FSM is coded in HDL as two concurrent blocks that execute under different conditions. One block evaluates the transition conditions, computes outputs and computes the next state variables. The other block updates the current state variables from the available next state and performs the actual state transitions. This second block is activated only on the trigger edge of the clock signal, or an asynchronous reset signal.
Stateflow sequential semantics map to HDL sequential statements, and local chart variables in function scope map to VHDL® variables in process scope. In VHDL, variable assignment is sequential. Therefore, statements in a Stateflow function that uses local variables can map to statements in a VHDL process that uses corresponding variables. The VHDL assignments execute in the same order as the assignments in the Stateflow function.