Hardware-in-the-Loop Implementation of Simscape Model on Speedgoat FPGA I/O Modules
This example shows how to synthesize and generate FPGA bitstream from a Simscape™ half-wave rectifier model and download the bitstream to a Speedgoat® FPGA I/O 334-325K target for Hardware-in-the-Loop (HIL) implementation.
Generate a HDL implementation model from the Simscape model by using the Simscape HDL Workflow Advisor. The HDL implementation model is a Simulink® model that replaces the Simscape algorithm with HDL-compatible blocks
Generate FPGA bitstream for the HDL implementation model by using the HDL Workflow Advisor
Download the bitstream to the Speedgoat FPGA I/O module by using the Simulink Real-Time Explorer for Hardware-in-the-Loop Simulation.
Half Wave Rectifier Model
Open the Simscape half wave rectifier model. In the MATLAB® command prompt, enter:
ModelName = 'sschdlexHalfWaveRectifierExample'; open_system(ModelName) set_param(ModelName, 'SimulationCommand', 'update');
The half-wave rectifier consists of a Resistor, which is a linear block, and a Diode, which is a switched linear block. At the input and output port interfaces, the model has Simulink-PS Converter and PS-Simulink Converter blocks. The solver settings are configured for compatibility with Simscape HDL Workflow Advisor. If you open the Block Parameters dialog box for the Solver Configuration block, Use local solver is selected and
Backward Euler is specified as the Solver type. See Get Started with Simscape Hardware-in-the-Loop Workflow.
To see the algorithm functionality, simulate the model.
sim(ModelName) open_system([ModelName, '/Scope'])
2. Configure the Simscape Model for HDL compatibility by using the
Generate HDL Implementation Model
To generate the HDL implementation model:
1. Open the Simscape HDL Workflow Advisor:
2. To compare functionality of the HDL implementation model with the original Simscape algorithm, select the Generate implementation model step, and then select the Generate validation logic for the implementation model check box. Use a Validation logic tolerance of
0.001. Right-click the Generate implementation model step and select Run to Selected Task.
The Advisor generates an HDL implementation model and a state-space validation model. To compare functionality of the HDL implementation model with the original Simscape algorithm, open and simulate the state-space validation model. The output of this model matches the original Simscape model. For a more systemic verification, see Validate HDL Implementation Model to Simscape Algorithm.
See also Simscape HDL Workflow Advisor Tasks.
Setup and Configuration
The Speedgoat IO334-325K FPGA module uses Xilinx® Vivado® and IP Core Generation workflow infrastructure. Before you deploy the HDL implementation model on the Speedgoat I/O module:
1. Install Xilinx Vivado and Setup Tool Path
Install the latest version of Xilinx® Vivado® as listed in HDL Language Support and Supported Third-Party Tools and Hardware. Then, set the tool path to the installed Xilinx Vivado executable by using the
2. Install Speedgoat I/O Blockset and Speedgoat - HDL Coder Integration Packages
To install the Speedgoat I/O Blockset and the Speedgoat - HDL Coder Integration packages. Go to Speedgoat documentation online at www.speedgoat.com/knowledge-center.
3. For real-time simulation, set up the development environment and target computer settings. See Get Started with Simulink Real-Time (Simulink Real-Time).
HDL Workflow Advisor
The HDL Workflow Advisor guides you through HDL code generation and the FPGA design process. Use the Advisor to:
Check the model for HDL code generation compatibility and fix incompatible settings.
Generate HDL code, test bench, and scripts to build and run the code and test bench.
Perform synthesis and timing analysis.
Deploy the generated code on SoCs, FPGAs, and Speedgoat I/O modules.
To open the HDL Workflow Advisor, use the
The left pane contains folders that represent a group of related tasks. Expanding the folders and selecting a task displays information about that task in the right pane. The right pane can contain simple controls for running the task to advanced parameters and option settings that control code and test bench generation. To learn more about each task, right-click that task, and select What's This?. See Getting Started with the HDL Workflow Advisor.
Generate FPGA Bitstream for Speedgoat Target Computer
1. Open the HDL implementation model, and then open the HDL Workflow Advisor for the implementation model.
open_system('gmStateSpaceHDL_sschdlexHalfWaveRectifierEx') hdladvisor('gmStateSpaceHDL_sschdlexHalfWaveRectifierEx/HDL Subsystem')
2. In Set Target Device and Synthesis Tool task, specify Target workflow as
Simulink Real-Time FPGA I/O and Target platform as
3. In the Set Target Reference Design task, select a value of
x4 for the parameter
PCIe lanes, and select Run This Task.
4. In Set Target Interface task, map the input and output
single data type ports to
PCIe Interface and select Run This Task.
5. In the Set Target Frequency task, set the Target Frequency (MHz) as
6. Right-click the Generate Simulink Real-Time Interface task and select Run to Selected Task to generate the HDL IP core, FPGA bitstream, and download the bitstream to the IO334 I/O module in the Speedgoat target computer.
A Simulink Real-Time Interface model is generated, and named as gm_gmStateSpaceHDL_sschdlexHalfWaveRectifierEx_slrt.
For rapid prototyping, you can export the Workflow Advisor settings to a script. The script is a MATLAB file that you run from the command line. You can modify and run the script, or import the settings into the HDL Workflow Advisor User Interface. To save the workflow, in the HDL Workflow Advisor User Interface, select File > Export to Script. Save the file as
To import this file, in the HDL Workflow Advisor User Interface, select File > Import from Script. In the Import Workflow Configuration dialog box, select the
hdlworkflow_slrt_IO334.m file. The HDL Workflow Advisor updates the tasks according to the imported script. See Run HDL Workflow with a Script.
Deploy Bitstream to Speedgoat IO334-325k Target
1. Connect Development Computer to Target
Connect the development computer to the target by using a cross-over network cable. The default IP address for the Speedgoat target computer is
192.168.7.5. Set the IP address of the communication link between the development computer and target computer to a value
192.168.7.2 because the communication link must be in the same network.
2. Setup and Configure Simulink Real-Time Explorer
You download the bitstream by using the Simulink Real-Time Explorer. To open the Simulink Real-Time Explorer, enter the command
slrtExplorer. Alternatively, you can open the Explorer from the Real-Time tab of the Simulink Toolstrip.
The Simulink Editor displays the Real-Time tab for models that are configured for the
slrealtime.tlc code generation target.
a. In Simulink Real-Time Explorer, on the Target Configuration tab, configure settings on the development computer:
Set IP Address as
192.168.7.5, or set as needed for a custom target computer IP address.
Set Name as
TargetPC1, or set as needed for a custom target computer name.
b. If you change the settings on the development computer, click the
Change IP Address button to apply corresponding changes on the target computer.
3. Create Real-Time Application
Open the Simulink Real-Time Interface model. Add a Scope block to the model and connect it to the outputs. Log the output signals to view the simulation results on the Simulation Data Inspector.
4. Build and Run Real-Time Application
Click the Run on Target button on the Real-Time tab to compile and download the model onto Speedgoat IO334-325k target.
Observe the output simulation results on the Simulation Data Inspector. The simulation results of the downloaded model match the original Simscape model simulation.