Open your model, and on the Apps tab, click HDL Verifier. Then, on the HDL Verifier tab, click C Code Settings. The Configuration Parameters dialog opens on the Code Generation pane.
At System target file, under Target
Selection, click Browse. Select
systemverilog_dpi_grt.tlc from the
Alternatively, if you have an Embedded Coder® license, you can select target
target enables you to access its additional code generation options
on the Code Generation pane of the Model
Configuration Parameters dialog box.
If you are generating a cross-platform component, you must select
systemverilog_dpi_ert.tlc for the
System target file parameter.
Still on the Code Generation pane, select a
Toolchain. To generate a shared library for the same
operating system as the host machine, select a compiler from the list of installed
compilers or select
Automatically locate an installed
toolchain. To use the compiler included with the HDL simulator, or
to generate a component for a different operating system, or to generate an HDL
simulator project rather than a shared library, select an HDL simulator and your
target operating system.
For cross-platform generation, select Package code and
artifacts to generate a
.zip file to port the
generated files to the target machine. See Generate Cross-Platform DPI Components.
You can optionally add additional compilation flags. Under Build
Specify. To display
the current flags, click Show Settings.
Complete this step if you designated internal signals in your model as test points and want to access them in the generated DPI component.
In the left pane, select Code Generation > Interface.
In the Generate C API for section, verify that the signals check box is selected.
Select Code Generation > SystemVerilog DPI.
For Generate access function to test point, select
One function per Test Point or
One function for all Test Points.
In the left pane, select Code Generation > SystemVerilog DPI.
Select Report run-time error to export run-time errors from Simulink® to your HDL simulation. Not all Simulink blocks provide run-time error checks. You can add run-time checks by adding an Assertion block to your Simulink model.
To generate a test bench, select Generate test bench. The test bench checks the generated C component against data vectors from your Simulink subsystem.
In the SystemVerilog Ports section:
Select the SystemVerilog data types. (optional)
Port list or
Composite data types. This option
struct data types for
any nonvirtual buses or for complex data types. Alternatively,
Flattened to create flattened
Click OK to accept these settings and to close the Configuration Parameters dialog box.
In your model, right-click the block containing the subsystem you want to generate the component from. Select Code > C/C++ Code > Build this Subsystem.
Click Build in the dialog box.
The SystemVerilog component is generated as
subsystem is the name of the subsystem from
which you generated the DPI component. This build also results in a
generated package file named
which includes all the function declarations for the component.
If you built the component for the host machine, you can now use the component. To copy the built component to another machine with the same operating system, copy these files:
Generated SystemVerilog wrapper,
Generated SystemVerilog package file,
Generated test bench folder,
To port the component to another machine with a different operating system, follow the instructions in Generate Cross-Platform DPI Components.