Decision feedback equalizer (DFE) with clock and data recovery (CDR)

**Library:**SerDes Toolbox / Datapath Blocks

The DFECDR block adaptively processes a sample-by-sample input signal or analytically processes an impulse response vector input signal to remove distortions at post cursor taps.

The decision feedback equalizer modifies baseband signals to minimize the intersymbol
interference (ISI) at the clock sampling time. The DFE samples data at each clock tick and
adjusts the amplitude of the waveform by a correction voltage. The correction voltage is
determined by the previous *N* sampled unit interval (UI) values, where
*N* is the number of DFE taps.

A clock and data recovery function provides the clock sampling location to the DFE. The clock recovery is a first order phase tracking CDR model. For more information, see Clock and Data Recovery in SerDes System.