Check for specified minimum and maximum value violations

R2026b

Check ID: mathworks.sldv.minmax

Detect signals that exceed specified minimum and maximum values.

Description

This analysis checks the specified minimum and maximum values (the design ranges) on intermediate signals throughout the model and on the output ports. If the analysis detects that a signal exceeds the design range, the results identify where in the model the errors occurred.

Following the recommendations of this check increases the likelihood of generating MISRA C:2012 compliant code for embedded applications, as well as code that complies with the CERT C and CWE standards.

Results and Recommended Actions

Result	Recommended Action
Failed, model incompatible	Resolve the model incompatibility. See Unsupported Simulink Blocks in Analysis (Simulink Design Verifier) Analysis Limitations and Considerations for Model Blocks (Simulink Design Verifier) Limitations of Simulink Design Verifier for Simulink Software Features (Simulink Design Verifier) Limitations of Simulink Design Verifier with Stateflow Features (Simulink Design Verifier) Simulink Design Verifier Limitations for MATLAB for Code Generation (Simulink Design Verifier) Also see Handle Model Complexities with Automatic Stubbing (Simulink Design Verifier).
Violation of minimum and/or maximum found in model	To view the conditions that cause the violation, create a harness model. When you simulate the harness with the given inputs, it replicates the error. Click View test case in the Model Advisor report.

Result

Recommended Action

Failed, model incompatible

Resolve the model incompatibility. See

Unsupported Simulink Blocks in Analysis (Simulink Design Verifier)
Analysis Limitations and Considerations for Model Blocks (Simulink Design Verifier)
Limitations of Simulink Design Verifier for Simulink Software Features (Simulink Design Verifier)
Limitations of Simulink Design Verifier with Stateflow Features (Simulink Design Verifier)
Simulink Design Verifier Limitations for MATLAB for Code Generation (Simulink Design Verifier)

Also see Handle Model Complexities with Automatic Stubbing (Simulink Design Verifier).

Violation of minimum and/or maximum found in model

To view the conditions that cause the violation, create a harness model. When you simulate the harness with the given inputs, it replicates the error. Click View test case in the Model Advisor report.

Capabilities and Limitations

Does not run on library models.
Analyzes content in masked subsystems. The input parameter Look inside masks is set to all. You can use a filter to exclude specific subsystems. For more information, see Filter Objectives by Using Simulink Design Verifier Filter Explorer (Simulink Design Verifier).
Analyzes content of library-linked blocks. The input parameter Follow links is set to on.
Does not support exclusions.