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Generate Test Cases for a Subsystem

You can analyze a subsystem within a model. This technique is good for large models, where you want to review the analysis in smaller, manageable reports. Following two methods help you to generate test cases for subsystem in different modes:

Generate Test Cases for Subsystems for Normal Mode

This example shows how to analyze the Controller subsystem in the sldvdemo_cruise_control model.

  1. Open the example model:

    openExample('sldv/CruiseControlTestGenerationExample',...
    'supportingFile', 'sldvdemo_cruise_control');
  2. Right-click the Controller subsystem, and select Design Verifier > Enable ‘Treat as Atomic Unit’ to Analyze.

    The Function Block Parameters dialog box for the Controller subsystem opens.

  3. Select Treat as atomic unit.

    An atomic subsystem executes as a unit relative to the parent model. Subsystem block execution does not interleave with parent block execution. You can extract atomic subsystems for use as standalone models.

    To analyze a subsystem with Simulink® Design Verifier™, set the Treat as atomic unit parameter.

    After you set the parameter, other parameters become available, but you can ignore them.

  4. To close the dialog box, click OK.

  5. On the Simulation tab, in the File section, select Save > Save As and save the Cruise Control Test Generation model with a new name.

  6. To start the subsystem analysis and generate test cases, right-click the Controller subsystem, and select Design Verifier > Generate Tests for Subsystem.

  7. The Simulink Design Verifier software analyzes the subsystem. When the analysis is complete, view the analysis results for the Controller subsystem by clicking one of the following options:

    • Highlight analysis results on model

    • View tests in Simulation Data Inspector

    • Detailed analysis report

    • Create harness model

    • Export test cases to Simulink Test

    • Simulate tests and produce a model coverage report

    Note

    After processing a certain number of objectives, if the analysis stops, or if the analysis times out, you can use the Test Generation Advisor to better understand which subsystems are causing the problem. For more information, see Use Test Generation Advisor to Identify Analyzable Components.

  8. Review the results of the subsystem analysis and compare the results to the results of the full-model analysis as described in Analyze a Model:

    • The subsystem analysis analyzes the Controller as a standalone model.

    • The Controller subsystem contains all the test objectives in the Cruise Control Test Generation model. Both the analyses generate the same test cases.

Generate Test Cases for Subsystems for Software-in-the-Loop Mode

This example shows how to generate test cases for atomic subsystems in software-in-the-loop (SIL) mode by using the sldv_cruise_control_ats model.

Open the example model: sldv_cruise_control_ats

model = 'sldv_cruise_control_ats';
open_system(model);  

1. In the Configuration Parameters window, click Code Generation and set System Target File to ert.tlc.

2. Set up the function packaging of the subsystem by right-clicking PI Controller > Block Parameters (Subsystem) > Code Generation > Function Packaging and set as Reusable function or Nonreusable function.

3. Click Hardware Implementation, then set Device vendor and Device type to the vendor and type of your SIL system. For this example, set Device vendor to Intel and Device type to x-86-32 (Linux).

  1. Generate the code for the target. For subsystem analysis in SIL mode, code needs to be generated before invoking test generation.

  2. If the test generation target is Code Generated as Top model, generate the code for the target by entering:

slbuild(model,'StandaloneCoderTarget');
### Starting build procedure for: sldv_cruise_control_ats
### Generating code and artifacts to 'Model specific' folder structure
### Generating code into build folder: /tmp/Bdoc23b_2361005_1507434/tp232739a1/sldv-ex49944916/sldv_cruise_control_ats_ert_rtw
### Invoking Target Language Compiler on sldv_cruise_control_ats.rtw
### Using System Target File: /mathworks/devel/bat/Bdoc23b/build/matlab/rtw/c/ert/ert.tlc
### Loading TLC function libraries
.......
### Initial pass through model to cache user defined code
.
### Caching model source code
.............................................................
### Writing header file sldv_cruise_control_ats_types.h
.
### Writing header file sldv_cruise_control_ats.h
### Writing header file rtwtypes.h
### Writing source file sldv_cruise_control_ats.c
### Writing header file sldv_cruise_control_ats_private.h
### Writing source file ert_main.c
.
### TLC code generation complete (took 8.44s).
### Saving binary information cache.
### Using toolchain: GNU gcc/g++ | gmake (64-bit Linux)
### Creating '/tmp/Bdoc23b_2361005_1507434/tp232739a1/sldv-ex49944916/sldv_cruise_control_ats_ert_rtw/sldv_cruise_control_ats.mk' ...
### Building 'sldv_cruise_control_ats': "/mathworks/devel/bat/Bdoc23b/build/matlab/bin/glnxa64/gmake"  -f sldv_cruise_control_ats.mk all
gcc -c -fwrapv -fPIC -O0 -DCLASSIC_INTERFACE=0 -DALLOCATIONFCN=0 -DTERMFCN=1 -DONESTEPFCN=1 -DMAT_FILE=0 -DMULTI_INSTANCE_CODE=0 -DINTEGER_CODE=0 -DMT=0  -DTID01EQ=0 -DMODEL=sldv_cruise_control_ats -DNUMST=1 -DNCSTATES=0 -DHAVESTDIO -DMODEL_HAS_DYNAMICALLY_LOADED_SFCNS=0 -I/tmp/Bdoc23b_2361005_1507434/tp232739a1/sldv-ex49944916 -I/tmp/Bdoc23b_2361005_1507434/tp232739a1/sldv-ex49944916/sldv_cruise_control_ats_ert_rtw -I/mathworks/devel/bat/Bdoc23b/build/matlab/extern/include -I/mathworks/devel/bat/Bdoc23b/build/matlab/simulink/include -I/mathworks/devel/bat/Bdoc23b/build/matlab/rtw/c/src -I/mathworks/devel/bat/Bdoc23b/build/matlab/rtw/c/src/ext_mode/common -I/mathworks/devel/bat/Bdoc23b/build/matlab/rtw/c/ert -o "sldv_cruise_control_ats.o" "/tmp/Bdoc23b_2361005_1507434/tp232739a1/sldv-ex49944916/sldv_cruise_control_ats_ert_rtw/sldv_cruise_control_ats.c"
gcc -c -fwrapv -fPIC -O0 -DCLASSIC_INTERFACE=0 -DALLOCATIONFCN=0 -DTERMFCN=1 -DONESTEPFCN=1 -DMAT_FILE=0 -DMULTI_INSTANCE_CODE=0 -DINTEGER_CODE=0 -DMT=0  -DTID01EQ=0 -DMODEL=sldv_cruise_control_ats -DNUMST=1 -DNCSTATES=0 -DHAVESTDIO -DMODEL_HAS_DYNAMICALLY_LOADED_SFCNS=0 -I/tmp/Bdoc23b_2361005_1507434/tp232739a1/sldv-ex49944916 -I/tmp/Bdoc23b_2361005_1507434/tp232739a1/sldv-ex49944916/sldv_cruise_control_ats_ert_rtw -I/mathworks/devel/bat/Bdoc23b/build/matlab/extern/include -I/mathworks/devel/bat/Bdoc23b/build/matlab/simulink/include -I/mathworks/devel/bat/Bdoc23b/build/matlab/rtw/c/src -I/mathworks/devel/bat/Bdoc23b/build/matlab/rtw/c/src/ext_mode/common -I/mathworks/devel/bat/Bdoc23b/build/matlab/rtw/c/ert -o "ert_main.o" "/tmp/Bdoc23b_2361005_1507434/tp232739a1/sldv-ex49944916/sldv_cruise_control_ats_ert_rtw/ert_main.c"
### Creating standalone executable ../sldv_cruise_control_ats ...
g++  -o ../sldv_cruise_control_ats sldv_cruise_control_ats.o ert_main.o  
### Created: ../sldv_cruise_control_ats
### Successfully generated all binary outputs.
gmake: Nothing to be done for `all'.
### Successful completion of build procedure for: sldv_cruise_control_ats
### Simulink cache artifacts for 'sldv_cruise_control_ats' were created in '/tmp/Bdoc23b_2361005_1507434/tp232739a1/sldv-ex49944916/sldv_cruise_control_ats.slxc'.

Build Summary

Top model targets built:

Model                    Action                        Rebuild Reason                                    
=========================================================================================================
sldv_cruise_control_ats  Code generated and compiled.  Code generation information file does not exist.  

1 of 1 models built (0 models already up to date)
Build duration: 0h 0m 32.489s

Note:

  • If the test generation target is Code Generated as Model Reference, generate the code for the target by entering:

% slbuild(model,'ModelReferenceCoderTargetOnly');
  • If there is a mismatch of the test generation target and the generated code interface target, then test generation returns an error.

  • If you generate a code for both targets, the test generation returns an error.

4. In the Apps tab, click Design Verifier. Then, in the Design Verifier tab, set Target to Code Generated as Top Model. Generate tests by using one of these methods:

  1. Right click the PI Controller block, then click Design Verifier > Generate Tests for Subsystems to generate tests.

  2. Select the PI Controller block by unpinning it from the toolstrip. Then click Generate Tests.

  3. Create a harness for the subsystem and then invoke test generation by right-clicking the PI Controller block, then clicking Test Harness > Create for PI Controller. Select the harness name and click OK.

Open the new harness. Then click Design Verifier and click Generate Tests.

Alternatively, you can use the API to generate the tests by entering:

opts = sldvoptions;

opts.TestgenTarget = Sldv.utils.Options.TestgenTargetGeneratedCodeStr;

[status, fileNames] = sldvrun(ssPath,opts,true);

5. Review the results of the subsystem analysis and compare the results to the results of the full-model analysis as described in Generate Test Cases for Subsystems for Normal Mode.