Multiprocessor Architecture Modeling

Design, evaluate, and implement multiprocessor architecture modeling

Partition algorithms for multicore execution with inter-processor data communication (IPC) and co-processor (control law accelerator) blocks. With processor-in-the-loop (PIL) simulation, you can cross-compile source code on your development computer, and then download and run the object code on the processor in the hardware board.

Map tasks and peripherals in a model to hardware board configurations using Hardware Mapping tool.

Blocks

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CLA

CLA Task Manager	Create and manage task executions in Control Law Accelerator (CLA) model (Since R2022a)
Software Trigger CPU<->CLA	Trigger software events between processor (CPU) and control law accelerator (CLA) (Since R2022a)

Interface

ADC Interface	Convert analog signal on ADC input pin to digital signal (Since R2020b)
PWM Interface	Simulate pulse width modulation (PWM) output from hardware (Since R2020b)

Driver

ADC Read	Read ADC data values from ADC Interface block (Since R2020b)
PWM Write	Send pulse width modulation (PWM) signal configuration to PWM Interface block (Since R2020b)

IPC

Interprocess Data Channel	Model interprocessor data channel between two processors (Since R2020b)
Interprocess Data Read	Receive messages from another processor using interprocess communication channel (Since R2020b)
Interprocess Data Write	Send messages to another processor using interprocessor data write (Since R2020b)

Scheduling

Task Manager

Create and manage task executions in Simulink model

Tools

SoC Builder	Build, load, and execute SoC model on SoC, FPGA, and MCU boards
Hardware Mapping	Map tasks and peripherals in a model to hardware board configurations (Since R2022b)

Topics

Processor-in-Loop (PIL) Simulation

PIL Simulation
Processor-in-the-Loop (PIL) simulation techniques for Texas Instruments hardware board.

Multiprocessor Modeling

Use C2000 blocks with Multiprocessor Modeling
Use multiprocessor modeling pass-though block simulation with C2000™ Microcontroller Blockset blocks.
Interprocess Data Communication via Dedicated Hardware Peripheral
Data communication methods between two or more processes within a single processor or across multiple connected processors.
Modeling and Code Generation Using Hardware Interrupt
Model and generate code using Hardware Interrupt block. For multiprocessor modeling use Task Manager block and Hardware Mapping tool.
Streaming Task Profiling
Use the streaming task profiler to measure tasks on the TI C2000 processor.
Run Multiprocessor Models in External Mode
Run a multiprocessor SoC model in external mode running on separate processors on the hardware board.
Modeling Control Law Accelerator (CLA) Using Model Reference
Use the control law accelerator (CLA) co-processor in C2000 MCU models.
Using ARM Cortex-M Coprocessor
Use the ARM^® Cortex^®-M coprocessor in C2000 MCU models.
Communication Between Cores Using IPC Blocks
Use the IPC blocks to communicate between cores in F2837xD and F2838x processors on the TI C2000 processor.

Featured Examples

Get Started with C2000 Multiprocessor Blocks on MCUs

Simulate and deploy a closed-loop feedback control algorithm on to a MCU using C2000™ Microcontroller Blockset.

Open Model

Partition Motor Control for Multiprocessor MCUs

Partition real-time motor control application on to multiple processors to achieve design modularity and improved control performance.

Open Model

Integrate MCU Scheduling and Peripherals in Motor Control Application

Identify and resolve issues with respect to peripheral settings and task scheduling early during development.

Open Model

Control Law Accelerator in DC-DC Power Conversion

Manage the voltage mode control (VMC) algorithm for a closed loop DC-DC power conversion system by using the Control Law Accelerator (CLA). An auxiliary software current protection loop is managed by C2000 CPU. In the TMS320F28379D and similar processor families, the CLAs execute the hard-realtime portions of the algorithm can connect with hardware peripherals such as ADC's and PWM's. The TI C2000 CPU is better suited for hard real-time portions of the algorithm that require multitasking, handling of asynchronous events, and communication with other cores. While this example extends the DC-DC buck converter developed in the DC-DC Buck Converter on MCU example, the strategy presented can be applied to any design where a resource intensive hard real-time process executes on the CLA and real-time multi-tasking processes run on C2000 CPU.Required Hardware

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