How to resolve an error stated as: "System Generator Cannot support triggered sample time in". while converting .mdl file to VHDL program.

I have designed a Black Box for unipolar to bipolar converter with a single clock and clock_enable input. I have connected a pn sequence generator to its input via a gateway. Output is a ufix_8_0. When I am trying to generate the corresponding VHDL file, I am getting an error stated as: "System Generator Cannot support triggered sample time in". Can you please tell me how to resolve this error step by step. I am new to using MATLAB/Simulink. Hence any help will be highly appreciated. Thank you in advance.

Answer 1

[Tim McBrayer]

The error you are receiving is being emitted by Xilinx System Generator, not by HDL Coder. You will need to either use the Xilinx documentation or contact Xilinx to resolve this issue.