HDL cosimulation output different from FPGA output

Hi,

I am working on a project implementing 16 QAM transmitter on a FPGA.I started by developing a simulink model followed by HDL code generation by HDL coder . My cosimulation of developed code with Model Sim works as per desired but when the same code was implemented in FPGA with same clock settings,the working was not as desired.I got an unsatisfactory constellation output. Someone please suggest me the reasons for such an occurence.

Krishnakumar

Answer 1

[Bharath Venkataraman]

To debug this, I suggest a few things:

1. Run the HDL code and the testbench in ModelSim to see if it passes. This will confirm that the HDL code matches the delays or changes you may have requested from HDL Coder.

2. You may be adding delays with pipelines or changing the algorithms for blocks in the HDL code generation process in your data path that change the phase of signal you are processing. To debug this, please click on the "Generated Validation Model" option in the HDL Code Generation tab of Configuration parameters (Ctrl+E in Simulink). Simulating the validation model will tell you if any additional delays or changes introduced for HDL implementation are causing problems. The top part of the valdiation model contains your design with any delays or changes for HDL implementation.

3. Create a cosimulation model - this will run the HDL code in ModelSim, and the rest of the simulation will be in ModelSim. You can enable this option during HDL code generation by checking on the "Cosimulation model for use with: ..." option under the Test Bench tab of the Configuration Parameters. I suggest that you use the From and Go To blocks to send intermediate values to the output so that you can look at these in Simulink and verify that your design is working as expected.