What is the difference between wr_dout and r_dout ports of a Dual-port RAM in the hdldemolib? Please give a detailed explanation (if possible with an example)

The link to the Dual-port RAM is here.

Dear community members, any help is appreciated. Thank you.

Answer 1

[Tim McBrayer]

This is straightforward. The Dual Port RAM has two address inputs; wr_addr and rd_addr. wr_dout is the contents of the address wr_addr, and rd_dout is the contents of the address rd_addr.

The documentation is quite short and clear as to the specific behavior of all the ports, and tradeoffs between the various RAM blocks.

 >> web(fullfile(docroot, 'simulink/slref/dualportram.html'))

[Bala Vignesh]

Dear McBrayer, Thank you for your answer. I have a very basic question. If wr_dout is the contents of the wr_addr and rd_dout is the contents of the address rd_addr then why not have wr1_addr and wr2_addr and call them both as write operation? Especially, while cascading RAM blocks, I would like to know when is rd used and when is wr used.

Bala

[Tim McBrayer]

There is only one write data port; you can only write one word of data at a time. This is why the ports are named the way that they are. The capability of the Simulink RAM blocks are specifically designed to match the synthesis templates that are shared by all major synthesis tools, so that the implementation maps to the underlying on-chip block RAMS.