Generate C code for FPGA

Hello,

Is it possible to generate C code for FPGA ? ( Atmel Arria V ) I only familiar with generaing c code for ARM, and generating HDL code for FPGA, but not "generate C code for FPGA". Is it possible ? Is there any tutorial on this subject ?

Thank you, Ran

Answer 1

[Wang Chen]

Hi Ran,

The recommended workflow is to use HDL Coder to generate HDL Code and IP core for Altera SoC FPGA fabric, and use Embedded Coder to generate C code to program the ARM processor on the same chip. Please see following pages for examples and videos:

• http://www.mathworks.com/hardware-support/altera-soc-hdlcoder.html
• http://www.mathworks.com/hardware-support/altera-soc-ecoder.html

Thanks, Wang

Answer 2

[Walter Roberson]

Using Simulink, Simulink Coder, MATLAB Coder, and (recommended) Fixed Point Designer, you can generate C code for a generic target. That will not generally be as optimized as if VHDL were generated.

[ran shalit]

Hi Walter,

I'm not sure I understand. Where is that C code running ? When we generate simulink code for ARM , it runs in ARM. When we generate HDL code for FPGA, then it runs in FPGA. But What does it mean generating C code for FPGA ? FPGA need HDL not C code, Right ?

Regards, Ran

[Walter Roberson]

You would have to compile the C code for your target, and the compiler would need to be able to generate whatever can be used by the FPGA (such as HDL or VHDL)

You might be interested in having a look at "X32 Soft Core" over here

The X32 is an experimental 32 bit soft core developed at our Embedded Software Lab. It propagates the idea that (for many embedded applications) processor design need not be a 9-figure project and that it can be done by anyone who knows how to write a VHDL byte code interpreter. We simply took lcc (a well-known ANSI C compiler) and wrote an interpreter for its intermediate byte code. No specific instruction set architectures, no backends, just a student's thesis job. To turn it into a truly reconfigurable microcontroller we added some I/O devices to show some principles involved. And it works! As all the software is free, we have a complete free embedded solution that runs on any FPGA that carries more than some 250k gates (which is about any FPGA nowadays). You are free to use the software outside of the course as long as you give proper credit to the authors and our lab. Note, however, that this free software is provided AS IS without any warranty whatsoever. Visit the X32 web site for more detailed information.

[ran shalit]

I'm not sure what you mean by "You would have to compile the C code for your target". Our customer want to generate by himself:

1. C code for ARM (in Arria V)
2. C code for FPGA (on same Arria).

1, I know C code for ARM can be generated (there are tutorial for it in mathworks), 2 I know that HDL can be generated (there are tutorial for it in mathworks), but not how to generate C code for FPGA. There is no such option in simulink.(and I found no tutorial for it in mathworks)

Thanks anyway,

Ran

[Walter Roberson]

After a bunch of further reading I see that the Arria is a Soc (System on a Chip) that combines an ARM processor with a FPGA. The software to use for the process is their Embedded Design Suite (EDS), which offers access to a couple of different tool chains. Two of the tool chains offer to compile down to "bare metal". A quick scan suggests that one of the two compilers (at least) is open source (free), but that using the debugging tools for the bare metal effectively requires that the advanced version of the EDS be licensed.

Both the ARM core and the FPGA appear to be programmed using C, and you can find a description of the processes in the EDS User Guide, from the beginning of chapter 4 to the point in that chapter where it starts talking about developing Linux applications.

The Mathworks produce Embedded Coder has a lot of flexibility, and I would think it fairly likely that it could generate C code that would be accepted by the tools described above. You might not even need Embedded Coder, just Simulink Coder; I am not familiar enough with the limits of Simulink Coder to say.

Note: I have no experience with any of these tools. I have been scanning the Coder documentation for a while and it looks like it could be done, but if there is a subtle limitation I would not know it.

[ran shalit]

Thank you Walter!