How can I use vhdl generics when I generate a matlab system object from my vhdl code with HDL verifier?
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Eduardo Lasarte on 18 Sep 2016
Commented: Eduardo Lasarte on 22 Sep 2016
I want to generate a matlab system object from my vhdl code with HDL verifier, for using it as FPGA in the loop. Following matlab documentation's steps is quite easy to do it. The problem is that my code contains vhdl generics. So, once matlab generates the system object, I would like to be able to change the value of the generics, but I don´t know how to do it.
Tao Jia on 21 Sep 2016
With FPGA-in-the-Loop, once you have generated the FPGA Programming File, the values of generics are fixed. You cannot change it just like you cannot change the FPGA circuit dynamically.
To change the generics, you need to go though FIL Wizard to regenerate the FPGA programming file, and this will give you a new System object. You should use the new System object instead of just modifying the old one.
Hope this helps, Tao
More Answers (1)
Tim McBrayer on 19 Sep 2016
It sounds like you are trying to model existing handwritten VHDL that uses generics in its interface, in Simulink, and using a System Object. And, the HDL Coder implementation of System Objects don't support generics.
One thing you could try is to wrap the System Object block inside a subsystem. This may help in one of two ways depending on your circumstances. If you are trying to black-box your existing VHDL code into a larger Simulink design, you can set the HDL Architecture of the Subsystem to a black box and connect the generics up through that interface. Alternatively, you can investigate using a masked subsystem and setting 'mask parameters as generics' in HDL Coder.
Find more on HDL Code Generation and Deployment in Help Center and File Exchange
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